ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 672
ALXD800EEXJ2VC C3
Manufacturer Part Number
ALXD800EEXJ2VC C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VC_C3.pdf
(680 pages)
Specifications of ALXD800EEXJ2VC C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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PFMAX Packed Floating-Point MAXimum
PFMIN Packed Floating - Point MINimum
PFMUL Packed Floating-Point Multiplication
PFNACC Packed Floating-Point Negative Accumulate
PFPNACC Packed Floating-Point Mixed Positive-Negative Accumulate
PFRCP Floating-Point Reciprocal Approximation
PFRCPV Floating-Point Reciprocal Vector
PFRCPIT1 Packed Floating-Point Reciprocal, First Iteration Step
PFRCPIT2 Packed Floating-Point Reciprocal/Reciprocal Square Root, Second Iteration Step
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX Register 1 with MMX Register2
MMX register1 with Mwnory64
MMX Register 1 with MMX Register 2
MMX Register with Memory64
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX Register1 with MMX Register
MMX Register with Memory64
MMX Register1 with MMX Register 2
MMX Register with Memory64
MMX Register 1 with MMX Register 2
MMX Register with Memory64
AMD 3DNow!™ Instructions
Table 8-30. AMD 3DNow!™ Technology Instruction Set (Continued)
33234H
0F0F [11 mm1
mm2] A4
0F0F [mod mm r/m]
A4
0F0F [11 mm1
mm2] 94
0F0F [mod mm r/m]
94
0F0F [11 mm1
mm2] B4
0F0F [mod mm 2]
B4
0F0F [11 mm1
mm2] 8A
0F0F [mod mm r/m]
8A
0F0F [11 mm1
mm2] 8E
0F0F [mod mm r/m]
8E
0F0F [11 mm1
mm2] 96
0F0F [mod mm r/m]
96
0F0F [11 mm1
mm2] 86
0F0F [mod mm r/m]
86
0F0F [11 mm1
mm2] A6
0F0F [mod mm r/m]
A6
0FDF [11 mm1
mm2] B6
0FDF [mod mm r/m]
B6
Opcode/imm8
MMX reg 1[dword] <--- MMX reg 1 [dword] --- if (MMX reg 1 [dword]
MMX reg 2 [dword])
MMX reg 1 [dword] <--- MMX reg 2 [dword] --- if (MMX reg 1 [dword]
NOT
MMX reg [dword] <--- MMX reg [dword] --- if (MMX reg [dword]
Memory64 [dword])
MMX reg [dword] <--- Memory [dword --- if (MMX reg [dword] NOT
Memory64 [dword])
MMX reg 1 [dword] <--- MMX reg 1 [dword] --- if (MMX reg 1 [dword]
MMX reg 2 [dword])
MMX reg 1 [dword] <--- MMX reg 1 [dword] --- if (MMX reg 1 [dword]
NOT
MMX reg [dword] <--- MMX reg [dword] --- if (MMX reg [dword]
Memory64 [dword])
MMX reg [dword] <--- Memory64 [dword] --- if (MMX reg [dword] NOT
<
MMX reg 1 [dword] <--- sat --- MMX reg 1 [dword] * MMX reg 2 [dword]
MMX reg [dword] <--- sat --- MMX reg [dword] * Memory64 [dword]
MMX reg 1 [low dword] <--- (MMX reg 1 [low dword] - MMX reg 1 [high
dword])
MMX reg 1 [high dword] <--- (MMX reg 2 [low dword] - MMX reg 2 [high
dword])
MMX reg [low dword] <--- (MMX reg [low dword] - MMX reg [high
dword])
MMX reg [high dword] <--- (Memory64 [low dword] - Memory64 [high
dword])
MMX reg 1 [low dword] <--- (MMX reg 1 [low dword] - MMX reg 1 [high
dword])
MMX reg 1 [high dword] <--- (MMX reg 2 [low dword] + MMX reg 2
[high dword])
MMX reg [low dword] <--- (MMX reg [low dword] - MMX reg [low
dword])
MMX reg [high dword] <--- (Memory64 [low dword] - Memory64 [high
dword])
MMX reg 1 [low dword] <--- sat --- reciprocal --- MMX reg 2 [low dword]
MMX reg 1 [high dword] <--- sat --- reciprocal --- MMX reg 2 [low
dword]
MMX reg [Low dword] <--- sat --- reciprocal --- Memory64 [low dword]
MMX reg [high dword] <--- sat --- reciprocal --- Memory64 [low dword]
MMX reg 1 [low dword] <---sat --- reciprocal --- MMX reg 2 [low dword]
MMX reg 1 [high dword] <--- sat --- reciprocal MMX reg 2 [high dword]
MMX reg [low dword] <---sat --- reciprocal Value - Memory64 [low
dword]
MMX reg [high dword] <--- sat --- reciprocal value - Memory64 [high
dword]
MMX reg 1 [dword] <--- move --- MMX reg 2 [dword]
MMX reg [dword] <-- move --- Memory64 [dword]
MMX reg 1 [dword] <--- move --- MMX reg 2 [dword]
MMX reg [dword] <--- move --- Memory64 [dword]
Memory64 [dword])
>
<
MMX reg 2 [dword])
MMX reg 2 [dword])
Operation
AMD Geode™ LX Processors Data Book
>
<
>
>
<
Instruction Set
Cnt
Clk
2
2
2
2
2
2
2
1
1
Notes
1, 2
1, 2
1
3
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