ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 664

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

664
PSHUFW Packed Shuffle Word
imm8
PSLLD Packed Shift Left Logical Dword
PSLLQ Packed Shift Left Logical Qword
PSLLW Packed Shift Left Logical Word
PSRAD Packed Shift Right Arithmetic Dword
PSRAW Packed Shift Right Arithmetic Word
PSRLD Packed Shift Right Logical Dword
PSRLQ Packed Shift Right Logical Qword
PSRLW Packed Shift Right Logical Word
MMX Register1, MMX Register2,
MMX Register, Memory64, imm8
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX Register 1 by MMX Register 2
MMX Register by Memory
MMX Register by immediate
MMX™ Instructions
33234H
Table 8-28. MMX™ Instruction Set (Continued)
0F70 [11 mm1 mm2]
#
0F70 [mod mm r/m]
#
0FF2 [11 mm1
mm2]
0FF2 [mod mm r/m]
0F72 [11 110 mm] #
0FF3 [11 mm1
mm2]
0FF3 [mod mm r/m]
0F73 [11 110 mm] #
0FF1 [11 mm1
mm2]
0FF1 [mod mm r/m]
0F71 [11 110mm] #
0FE2 [11 mm1
mm2]
0FE2 [mod mm r/m]
0F72 [11 100 mm] #
0FE1 [11 mm1
mm2]
0FE1 [mod mm r/m]
0F71 [11 100 mm] #
0FD2 [11 mm1
mm2]
0FD2 [mod mm r/m]
0F72 [11 010 mm] #
0FD3 [11 mm1
mm2]
0FD3 [mod mm r/m]
0F73 [11 010 mm] #
0FD1 [11 mm1
mm2]
0FD1 [mod mm r/m]
0F71 [11 010 mm] #
Opcode
MMX reg 1 [word] <--- MMX reg 2 [windexall (imm8)]
MMX reg [word] <--- Memory64 [windexall (imm8)]
MMX reg 1 [dword] <--- MMX reg 1 [dword] shift left by MMX
reg 2 [dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword] shift left by
memory [dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword] shift left by [im byte],
shifting in zeroes
MMX reg 1 [qword] <--- MMX reg 1 [qword] shift left by MMX
reg 2 [qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword] shift left by memory
[qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword]shift left by [im byte],
shifting in zeroes
MMX reg 1 [word] <--- MMX reg 1 [word] shift left by MMX reg
2 [word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift left by memory
[word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift left by [im byte],
shifting in zeroes
MMX reg 1 [dword] <--- MMX reg 1 [dword] shift right by MMX
reg 2 [dword], shifting in sign bits
MMX reg [dword] <--- MMX reg [dword] shift right by memory
[dword], shifting in sign bits
MMX reg [dword] <--- MMX reg [dword] shift right by [im byte],
shifting in sign bits
MMX reg 1 [word] <--- MMX reg 1 [word] shift right by MMX
reg 2 [word], shifting in sign bits
MMX reg [word] <--- MMX reg [word] shift right by memory
[word], shifting in sign bits
MMX reg [word] <--- MMX reg [word] shift right by [im byte],
shifting in sign bits
MMX reg 1 [dword] <--- MMX reg 1 [dword] shift right by MMX
reg 2 [dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword] shift right by mem-
ory[dword], shifting in zeroes
MMX reg [dword] <--- MMX reg [dword]shift right by [im byte],
shifting in zeroes
MMX reg 1 [qword] <--- MMX reg 1 [qword] shift right by MMX
reg 2 [qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword] shift right by memory
[qword], shifting in zeroes
MMX reg [qword] <--- MMX reg [qword] shift right by [im byte],
shifting in zeroes
MMX reg 1 [word] <--- MMX reg 1 [word] shift right by MMX
reg 2 [word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift right by memory
[word], shifting in zeroes
MMX reg [word] <--- MMX reg [word] shift right by imm [word],
shifting in zeroes
Operation
AMD Geode™ LX Processors Data Book
Clock Ct
Instruction Set
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
2
2
2
Notes