ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 632

no-image

ALXD800EEXJ2VC C3

Manufacturer Part Number
ALXD800EEXJ2VC C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJ2VC C3

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
8.2.2.4
Extended function 80000005h (EAX = 80000005h) of the CPUID instruction returns information on the internal L1 cache
and TLB structures. They are used for reporting purposes only. See Table 8-23 for returned contents.
8.2.2.5
Extended function 80000006h (EAX = 80000006h) of the CPUID instruction returns information on the internal L2 cache
and TLB structures. See Table 8-24 on page 632 for returned contents.
.
632
Register
EAX
EBX
ECX
EDX
Register
EAX
EBX
ECX
EDX
CPUID Instruction with EAX = 80000005h
CPUID Instruction with EAX = 80000006h
FF10FF10h
0000F004h
00000000h
40100120h
40100120h
00002040h
00804120h
00000000h
Returned
Returned
Contents
Contents
33234H
Description
4 MB L1 TLB Information
4 KB L1 TLB Information
L1 Data Cache Information
L1 Code Cache Information
Description
L2 TLB Information
L2 TLB Information
L2 Code Cache Information
L2 Data Cache Information
Table 8-23.
Table 8-24.
CPUID Instruction with EAX = 80000005h
CPUID Instruction with EAX = 80000006h
Comment
Indicates no 4 MB L1 TLB.
Decodes to eight fully associative code TLB and eight
fully associative data TLB entries.
Indicates 16 KB four-way associative with 32-byte lines
for data cache. These encodings follow the AMD report-
ing method.
Indicates 16 KB four-way associative with 32-byte lines
for code cache. These encodings follow the AMD report-
ing method.
Comment
Two-way associative 64 entry code and data combined
TLB.
Indicates no L2 cache.
AMD Geode™ LX Processors Data Book
Instruction Set

Related parts for ALXD800EEXJ2VC C3