ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 550
ALXD800EEXJ2VC C3
Manufacturer Part Number
ALXD800EEXJ2VC C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VC_C3.pdf
(680 pages)
Specifications of ALXD800EEXJ2VC C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Bit
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Name
SDCLK_SET
DDR_RLE
SDCLK_DIS
TLA1_OA
D_TLA1
D_TLA0
D_DQ_E
D_DQ_O
RSVD
D_SDCLK
D_CMD_O
D_CMS_E
D_MA_O
D_MA_E
D_PCI_O
D_PCI_E
D_DOTCLK
D_DRBG_O
D_DRGB_E
D_PCI_IN
D_TDBGI
D_VIP
D_VIPCLK
H_SDCLK
PLL_FD_DEL
RSVD
DLL_OV
DLL_OVS/RSDA
33234H
GLCP_DELAY_CONTROLS Bit Definition (Continued)
Description
SDCLK Setup.
0: Full SDCLK setup.
1: Half SDCLK setup for control signals.
DDR read latch enable position.
SDCLK disable [1,3,5].
0: All SDCLK output.
1: SDCLK[4,2,0] output only.
TLA hint pin output adjust.
Output delay for TLA1.
Output delay for TLA0.
Output delay for DQ, DQM - even byte lanes.
Output delay for DQ, DQM - odd byte lanes.
Reserved.
Output delay for SDCLK.
Output delay for CKE, CS, RAS, CAS, WE - odd bits.
Output delay for CKE, CS, RAS, CAS, WE - even bits.
Output delay for BA and MA - odd bits.
Output delay for BA and MA - even bits.
Output delay for pci_ad, IRQ13, SUSPA#, INTA# - odd bits.
Output delay for pci_ad, CBE#, PAR, STOP#, FRAME#, IRDY#, TRDY#, DEVSEL#,
REQ#, GNT# - even bits.
Output delay for DOTCLK.
Output delay for DRGB[31:0] - odd bits.
Output delay for DRGB[31:0], HSYNC, VSYNC, DISPEN, VDDEN, LDE_MOD - even
bits.
Input delay for AD[31:0], CBE#, PAR, STOP#, FRAME#, IRDY#, TRDY#, DEVSEL#,
REQ#, GNT#, CIS.
Input delay for TDBGI.
Input delay for VID[15:0], VIP_HSYNC, VIP_VSYNC.
Input delay for VIPCLK.
Half SDCLK hold select (for cmd addr).
1: Half SDCLK setup for MA and BA signals.
0: Full SDCLK setup.
PLL Feedback Delay.
00: No feedback delay.
11: Max feedback delay.
(01: ~350 ps, 10: ~700 ps, 11: ~1100 ps).
Reserved.
DLL Override (to DLL).
DLL Override Setting or Read Strobe Delay Adjust.
When DLL Override is 1 this is the DQS overide delay.
When DLL Override is 0 this is the offset adjust value.
GeodeLink™ Control Processor Register Descriptions
AMD Geode™ LX Processors Data Book
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