ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 35

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Definitions
3.4.3
AMD Geode™ LX Processors Data Book
Signal Name
SDCLK[5:0]P,
SDCLK[5:0]N
MVREF
CKE[1:0]
CS[3:0]#
RAS[1:0]#
CAS[1:0]#
WE[1:0]#
BA[1:0]
MA[13:0]
TLA[1:0]
DQS[7:0]
Memory Interface Signals (DDR)
D20, D21,
D23, D24,
M28, L28,
B23, C19,
D30, F29,
See Table
J28, H28,
D27, C26
A28, C27
C20, D26
N31, J29,
F28, B28
E29, E28
B13, B15
A10, C6,
Ball No.
page 30
J4, H4,
H3, M2
M4, L4
F4, E4
3-6 on
P1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
up to 200 MHz
up to 200 MHz
Analog
f
V
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
MEM
V
Description
SDRAM Clock Differential Pairs. The SDRAM
devices sample all the control, address, and
data based on these clocks. All clocks are dif-
ferential clock outputs.
Memory Voltage Reference. This input oper-
ates at half the V
Clock Enable. For normal operation, CKE is
held high. CKE goes low during Suspend.
CKE0 is used with CS0# and CS1#. CKE1 is
used with CS2# and CS3#.
Chip Selects. The chip selects are used to
select the module bank within the system mem-
ory. Each chip select corresponds to a specific
module bank.
If CS# is high, the bank(s) do not respond to
RAS#, CAS#, or WE# until the bank is selected
again.
Row Address Strobe. RAS#, CAS#, WE#, and
CKE are encoded to support the different
SDRAM commands. RAS0# is used with CS0#
and CS1#. RAS1# is used with CS2# and
CS3#.
Column Address Strobe. RAS#, CAS#, WE#,
and CKE are encoded to support the different
SDRAM commands. CAS0# is used with CS0#
and CS1#. CAS1# is used with CS2# and
CS3#.
Write Enable. RAS#, CAS#, WE#, and CKE
are encoded to support the different SDRAM
commands. WE0# is used with CS0# and
CS1#. WE1# is used with CS2# and CS3#.
Bank Address Bits. These bits are used to
select the component bank within the SDRAM.
Memory Address Bus. The multiplexed row/
column address lines driven to the system
memory.
Supports 256-Mbit SDRAM.
Memory Debug Pins. These pins provide use-
ful memory interface debug timing signals.
(Should be wired to DIMM slot.)
TLA[0] is wired to DQS[8] on the DIMM
TLA[1] is wired to CB[0] on the DIMM
DDR Data Strobe.
MEM
33234H
voltage.
35