ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 621

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Instruction Set
8.1.2
The opcode field specifies the operation to be performed by the instruction. The opcode field is either one or two bytes in
length and may be further defined by additional bits in the mod r/m byte. Some operations have more than one opcode,
each specifying a different form of the operation. Certain opcodes name instruction groups. For example, opcode 80h
names a group of operations that have an immediate operand and a register or memory operand. The reg field may appear
in the second opcode byte or in the mod r/m byte.
The opcode may contain w, d, s, and eee opcode fields, for example, as shown in Table 8-26 on page 634.
8.1.2.1
When used, the 1-bit w field selects the operand size during 16-bit and 32-bit data operations. See Table 8-4.
8.1.2.2
When used, the 1-bit d field determines which operand is taken as the source operand and which operand is taken as the
destination. See Table 8-5.
8.1.2.3
When used, the 1-bit s field determines the size of the immediate data field. If the s bit is set, the immediate field of the
opcode is 8 bits wide and is sign-extended to match the operand size of the opcode. See Table 8-6.
AMD Geode™ LX Processors Data Book
0 (or not present)
d Field
0
1
s Field
w Field
Opcode
w Field (Operand Size)
d Field (Operand Direction)
s Field (Immediate Data Field Size)
1
0
1
Direction of Operation
8-Bit Operand Size
Register-to-Register
Register-to-Memory
Register-to-Register
Memory-to-Register
8 bits
8 bits
16-Bit Data Operations
or
or
Table 8-4. w Field Encoding
Table 8-5. d Field Encoding
Table 8-6. s Field Encoding
16 bits
8 bits
8 bits (sign-extended)
16-Bit Operand Size
Immediate Field Size
Operand Size
mod ss-index-base
Source Operand
16 bits
mod r/m
reg
or
32-Bit Data Operations
33234H
8 bits (sign-extended)
32-Bit Operand Size
32 bits
Destination Operand
8 bits
mod ss-index-base
mod r/m
32 bits
reg
or
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