ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 184

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.5.2.90 Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR)
MSR Address
Type
Reset Value
This register is reserved. Write as read.
184
19:14
11:9
Bit
3:2
13
12
8
7
6
5
4
1
0
Name
RSVD
CLK_ONS
SUSP
RSVD
RTSC_SUSP
RSVD
TSC_DMM
TSC_SUSP
TSC_SMM
RSVD
ISNINV
SNOOP
00001901h
R/W
00000000_00000000h
33234H
BC_CONFIG0_MSR Bit Descriptions (Continued)
Description
Reserved. Write as read.
CPU Core Clocks On during Suspend.
0: All CPU Core clocks off during Suspend. (Default)
1: All CPU Core clocks on during Suspend.
Suspend Active. Enable Suspend input.
0: Ignore Suspend input. (Default)
1: Enable Suspend input.
Reserved. Write as read.
Real Time Stamp Counter Counts during Suspend.
0: Disable.
1: Enable. (Default)
Reserved. Write as read.
Time Stamp Counter Counts during DMM.
0: Disable. (Default)
1: Enable.
Time Stamp Counter Counts during Suspend.
0: Disable. (Default)
1: Enable.
Time Stamp Counter Counts during SMM.
0: Disable.
1: Enable. (Default)
Reserved. Write as read.
Ignore Snoop Invalidate. Allow the CPU Core to ignore the INVALIDATE bit in the GLIU
snoop packet. When a snoop hits to a dirty cache line it is evicted, regardless of the state
of the INVALIDATE bit in the GLIU packet.
0: Process snoop packet.
1: Ignore snoop packet. (Default)
Instruction Memory (IM) to Data Memory (DM) Snooping. Allow code fetch snoops
from the IM to the DM cache.
0: Disable.
1: Enable. (Default)
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions