ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 369
ALXD800EEXJ2VC C3
Manufacturer Part Number
ALXD800EEXJ2VC C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VC_C3.pdf
(680 pages)
Specifications of ALXD800EEXJ2VC C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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Display Controller Register Descriptions
6.6.19.21 Vertical Display Enable End
Index
Type
Reset Value
6.6.19.22 Offset
Index
Type
Reset Value
6.6.19.23 Underline Location
Index
Type
Reset Value
AMD Geode™ LX Processors Data Book
Bits
Bit
7:0
7:0
Bit
4:0
7
6
5
Name
V_DISP_EN_
END
Name
OFST
Name
RSVD
DW
RSVD
UL
12h
R/W
00h
13h
R/W
00h
14h
R/W
00h
Vertical Display Enable End Register Bit Descriptions
Description
Offset. This field specifies the logical line width of the screen. This value (multiplied by
two or four depending on the CRTC clocking mode) is added to the starting address of
the current scan line to get the starting address of the next scan line.
Description
Reserved.
Doubleword Mode. When this bit is a 1, CRTC memory addresses are DWORD
addresses, and the CRTC refresh counter effectively increments by 4. When this bit is a
0, the address increment is determined by the Byte Mode bit in the CRTC Mode Control
register (Index 17h[6]).
Not Implemented. (Count by 4)
Underline Location. This field specifies the row scan value where the underline appears
in the character box in text modes.
Description
Vertical Display Enable End Register Bits [7:0]. This is a 10-bit value that specifies
the scan line where the vertical display enable signal goes inactive. It represents the
number of active scan lines minus 1. Bits 9 and 8 of this value are in the Overflow regis-
ter (Index 07h[6,1]).
Underline Location Register Bit Descriptions
Offset Register Bit Descriptions
33234H
369
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