ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 517

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Security Block Register Descriptions
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:37
34-33
31:3
Bit
2:1
36
35
32
4
3
0
RSVD
Name
RSVD
RB_ERR_
STATUS
RA_ERR_
STATUS
RSVD
AES_ERR_
STATUS
RB_ERR_
MASK
RA_ERR_
MASK
RSVD
AES_ERR_
MASK
Description
Reserved.
Response B Error Status. When set, this bit indicates that context B received a
response with either the SSMI or Exception flag set. This can occur on any of the read
responses or on the last write of an encrypt or decrypt operation that also requires a
response. If the error occurs on a read response, the operation is terminated and the
state machine returns to idle and signals completion. Write a one to this bit to clear the
status.
Response A Error Status. When set, this bit indicates that context A received a
response with either the SSMI or Exception flag set. This can occur on any of the read
responses or on the last write of an encrypt or decrypt operation that also requires a
response. If the error occurs on a read response, the operation is terminated and the
state machine returns to idle and signals completion. Write a one to this bit to clear the
status.
Reserved.
AES Error Status. Reserved Type. This bit is set if the module receives a transaction
identified with a reserved transaction type. This implies a hardware error.
0: AES Error not pending.
1: AES Error pending.
Writing a 1 to this bit clears the status.
Reserved.
Response B Error Mask. When set, this bit masks the Response B Error (bit 36) and
prevents generation of the error output. When cleared, the error is enabled and asser-
tion of Response B Error will generate an error.
Response A Error Mask. When set, this bit masks the Response A Error (bit 35) and
prevents generation of the error output. When cleared, the error is enabled and asser-
tion of Response A Error will generate an error.
Reserved.
AES Error Mask. Reserved Type.
0: Unmask the Error (enabled).
1: Mask the Error (disabled).
GLD_MSR_Error Bit Descriptions
GLD_MSR_ERROR Register Map
RSVD
RSVD
9
8
33234H
7
6
5
4
3
RSVD
2
RSVD
1
517
0