ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 120

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

120
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
V
63:32
30:22
21:20
19:16
63:21
19:17
15:12
15:8
11:9
Bit
7:0
Bit
7:6
5:4
3:1
31
20
16
8
0
Name
RSVD
V
LIP
RSVD
STRENGTH
TYPE
END
Name
RSVD
PNTKN
RSVD
VLD
LEN
RSVD
PTKEN
RSVD
TYPE
RSVD
LRU
RSVD
LIP
IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Tag
33234H
IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Tag
IF_TEST_DATA_MSR Bit Descriptions for Tag RAMs
IF_TEST_DATA_MSR Register Map for Tag RAMs
Description
Reserved.
Tag is Valid. (Default = 0)
Linear Address Bits [19:11].
Reserved.
Prediction Strength. Bit 19 = STRENGTH3, bit 18 = STRENGTH2, bit 17 =
STRENGTH1, and bit 16 = STRENGTH0.
0: Weakly predicted.
1: Strongly predicted.
COF Type. Bits [15:14] = TYPE3, bits [13:12] = TYPE2, bits [11:10] = TYPE1, and bits
[9:8] = TYPE0.
Predicted Taken COF End Markers.
Description
Reserved.
Predicted Not Taken. Entry ends with a predicted not-taken change of flow.
Reserved.
Valid. If an entry is valid, then all the tag information as well as the entry’s address and
target must also be valid. (Default = 0)
Number of Bytes. Number of bytes from address to either end of QWORD or end of pre-
dicted taken change of flow (0-8).
Reserved.
Predicted Taken. Entry ends with a predicted taken change of flow.
Reserved.
Change of Flow Type.
Reserved.
Next Entry. Indicates that entry is the next entry to be written. Exactly one of the four
entries should have this bit set.
RSVD
STRENGTH
RSVD
RSVD
RSVD
LEN
TYPE
RSVD
AMD Geode™ LX Processors Data Book
9
9
8
8
CPU Core Register Descriptions
RSVD
7
7
6
6
TYPE
5
5
4
4
END
3
3
RSVD
2
2
1
1
0
0