ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 178

• Manufacturer Part Number: ALXD800EEXJ2VC C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VC C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.5.2.83 L1 Data TLB Entry with Increment MSR (L1DTLB_ENTRY_I_MSR)
MSR Address
Type
Reset Value
Bit descriptions for this register are the same as for MSR 0000189Ah, except read/write of this register causes an auto-
increment on the L1 TLB_INDEX_MSR (MSR 00001898h).
5.5.2.84 L2 TLB/DTE/PTE Index MSR (L2TLB_INDEX_MSR)
MSR Address
Type
Reset Value
178
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
If SEL (bits [17:16]) = 0x
If SEL (bits [17:16]) = 1x
63:18
17:16
63:18
17:16
15:6
Bit
5:1
0
Name
RSVD (RO)
SEL
RSVD (RO)
INDEX
WAY
RSVD (RO)
SEL
0000189Bh
R/W
00000000_00000000h
0000189Ch
R/W
00000000_00000000h
33234H
RSVD
Description
Reserved (Read Only). (Default = 0)
Select Array to Access.
0x: L2 TLB (64 entries, values 0-63).
10: DTE cache (12 entries, values 0-11).
11: 4M PTE cache (4 entries, values 0-3).
Reserved (Read Only). (Default = 0)
L2 TLB Index. Post-increments on an access to L2TB_ENTRY_I_MSR (MSR
0000189Fh) if WAY (bit 0) = 1.
Way to Access. Toggles on each access to L2TB_ENTRY_I_MSR (MSR 0000189Fh).
Reserved (Read Only). (Default = 0)
Select Array to Access.
0x: L2 TLB (64 entries, values 0-63).
10: DTE cache (12 entries, values 0-11).
11: 4M PTE cache (4 entries, values 0-3).
PHYSADDR
LINADDR
L1DTLB_ENTRY_I_MSR Register Map
L2TLB_INDEX_MSR Bit Descriptions
L2TLB_INDEX_MSR Register Map
SEL
RSVD
RSVD
RSVD
AMD Geode™ LX Processors Data Book
9
9
8
8
RSVD
CPU Core Register Descriptions
7
7
6
6
5
5
4
4
INDEX
INDEX
3
3
2
2
1
1
0
0