ALXD800EEXJ2VC C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VC C3 Datasheet - Page 495

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ALXD800EEXJ2VC C3

Manufacturer Part Number
ALXD800EEXJ2VC C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJ2VC C3

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
Video Input Port Register Descriptions
6.10.2.5 VIP Current/Target (VIP_CUR_TAR)
VIP Memory Offset 10h
Type
Reset Value
6.10.2.6 VIP Max Address (VIP_MAX_ADDR)
VIP Memory Offset 14h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:16
15:0
31:3
Bit
Bit
2:0
Name
LINE_TARGET
CURRENT_
LINE (RO)
Name
MAX_ADDR
RSVD
R/W
00000000h
R/W
FFFFFFFFh
LINE_TARGET
Description
Line Target. Indicates the video line to generate an interrupt on.
Current Line (Read Only). Indicates the video line currently being captured. Line count-
ing begins on the first active line.
The count indicated in this field is reset to 0 at the start of each field (interlaced) or frame
(non-interlated).
Description
Max Address. This value is compared with the GLIU address. If the GLIU address is
equal or greater then this value, a VIP addressing error is detected. This resets the
RUN_MODE bits (VIP Memory Offset 00h[7:5]) to 000, stopping the VIP from capturing
data. A frame error INT is also generated. The A_ERR_EN bit (VIP Memory Offset
04h[30])must be set to enable this function. The VIP must be reset by writing a 1 to the
VRST bit (VIP Memory Offset 00h[0]) to clear the addressing error. Bits [2:0] of this regis-
ter are not used in the comparison. Note that the VIP will only stop capturing data on this
address, it will continue writing data from the FIFO into memory. Up to 192 QWORDs
(1536 bytes) can be written past this address (max # data in FIFO, although it is more
likely that ~10-20 QWORDs are written.
Reserved. Set to 0.
VIP_CUR_TAR Register Bit Descriptions
VIP_MAX_ADDR Bit Descriptions
VIP_MAX_ADDR Register Map
VIP_CUR_TAR Register Map
MAX_ADDR
CURRENT_LINE
9
9
8
8
33234H
7
7
6
6
5
5
4
4
3
3
2
2
RSVD
1
1
495
0
0

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