EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 162
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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High-Speed Differential I/O Support
Figure 2–74. Fast PLL & Channel Layout in the EP1S10, EP1S20 or EP1S25 Devices
Notes to
(1)
(2)
(3)
2–138
Stratix Device Handbook, Volume 1
Wire-bond packages support up to 624 Mbps.
See
There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for
“low” speed channels, as labeled in the device pin-outs at www.altera.com.
Transmitter Channels (2)
Transmitter Channels (2)
Up to 20 Receiver and
Up to 20 Receiver and
Table 2–41
Figure
Transmitter
Transmitter
Receiver
Receiver
2–74:
CLKIN
CLKIN
for the number of channels each device supports.
The Quartus II MegaWizard
implementation of up to 20 receiver or 20 transmitter channels for each
fast PLL. These channels operate at up to 840 Mbps. The receiver and
transmitter channels are interleaved such that each I/O bank on the left
and right side of the device has one receiver channel and one transmitter
channel per LAB row.
in EP1S10, EP1S20, and EP1S25 devices.
and channel layout in the EP1S30 to EP1S80 devices.
PLL 1
PLL 2
Fast
Fast
(3)
Figure 2–74
(3)
®
Plug-In Manager only allows the
shows the fast PLL and channel layout
PLL 4
PLL 3
Fast
Fast
Figure 2–75
Note (1)
Up to 20 Receiver and
Transmitter Channels (2)
Up to 20 Receiver and
Transmitter Channels (2)
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
shows the fast PLL
Altera Corporation
July 2005
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