EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 534
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 534 of 864
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Software Support
5–62
Stratix Device Handbook, Volume 2
Deserialization Factor
Use the What is the deserialization factor? parameter to specify the
number of bits per channel. The Stratix LVDS receiver supports 4, 7, 8,
and 10 for deserialization factor (J) values. Based on the factor specified,
the Quartus II software determines the multiplication and/or division
factor for the LVDS PLL to deserialize the data.
See
for the n
LSB (rx_out bit [J
total width of the receiver rx_out port is equal to the number of channels
multiplied by your deserialization factor.
Input Data Rate
The What is the inclock boost(W)? parameter sets the data rate coming
into the receiver and is usually the deserialization factor (J) multiplied by
the inclock frequency. This parameter’s value must be larger than the
input clock frequency and has a maximum input data rate of 840 Mbps
for Stratix devices. You do not have to provide a value for the inclock
boost (W) when designing with Stratix devices because the Quartus II
software can calculate it automatically from this parameter and the clock
frequency or clock period.
The rx_outclock frequency is (W/J)
data coming out of the receiver has the same frequency as the
rx_outclock port. The clock-to-data alignment of the parallel data
output from the receiver depends on the What is the alignment of data
with respect to rx_inclock? parameter.
Data Alignment with Clock
The What is the alignment of data with respect to rx_inclock? parameter
adjusts the clock-to-data skew. For most applications, the data is source
synchronous to the clock. However, there are applications where you
must center-align the data with respect to the clock. You can use the What
is the alignment of data with respect to rx_inclock? parameter to align
the input data with respect to the rx_inclock port. The MegaWizard
Plug-In automatically calculates the phase for the fast PLL outputs from
the What is the alignment of data with respect to rx_inclock? parameter.
This parameter’s default value is EDGE_ALIGNED, and other values
available from the pull-down menu are EDGE_ALIGNED,
CENTER_ALIGNED, 45_DEGREES, 135_DEGREES, 180_DEGREES,
225_DEGREES, 270_DEGREES, and 315_DEGREES. CENTER_ALIGNED
is the same as 90 degrees aligned and is useful for applications like
HyperTransport technology.
Table 5–5
th
channel spans from the MSB (rx_out bit [(J
for the differential bit naming convention. The parallel data
×
(n – 1)]), where J is the deserialization factor. The
×
input frequency. The parallel
Altera Corporation
×
n) – 1]) to the
July 2005
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