EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 591
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Basic FIR Filter Implementation Results
Table 7–6
FIR filter as shown in
Basic FIR Filter Design Example
Download the Basic FIR Filter (base_fir.zip) design example from the
Design Examples section of the Altera web site at www.altera.com.
Time-Domain Multiplexed FIR Filters
A TDM FIR filter is clocked n-times faster than the sample rate in order to
reuse the same hardware. Consider the 8-tap filter shown in
The TDM technique can be used with a TDM factor of 2, i.e., n = 2, to
implement this filter using only four multipliers, provided the filter is
clocked two times faster internally.
To understand this concept, consider
with a TDM factor of 2. A 2 -multiplied clock is required to run the filter.
On cycle 0 of the 2 clock, the user loads four coefficients into the four
multiplier inputs. The resulting output is stored in a register. On cycle 1
of the 2 clock, the user loads the remaining four coefficients into the
multiplier inputs. The output of cycle 1 is added with the output of cycle
0 to create the overall output. See the
page 7–14
The TDM implementation shown in
multipliers to achieve the functionality of an 8-tap filter. Thus, TDM is a
good way to save logic resources, provided the multipliers can run at n-
times the clock speed. The coefficients can be stored in ROM/RAM, or
any other muxing scheme.
Part
Utilization
Performance
Table 7–6. Basic FIR Filter Implementation Results
shows the results of the serial implementation of an 18-bit 8 tap
section for details on the coefficient loading schedule.
EP1S10F780
LCELL: 130/10570 (1%)
DSP Block 9-bit elements: 16/48 (33%)
Memory bits: 288/920448 (<1%)
247 MHz
Figure 7–5 on page 7–11
Figure 7–7
Figure 7–7
“TDM Filter Implementation” on
Stratix Device Handbook, Volume 2
requires only four
that shows a TDM filter
Figure
7–2.
7–13
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