EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 444
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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High-Speed Interfaces
4–16
Stratix Device Handbook, Volume 2
10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft
Standard P802.3ae/D2.0
10 Gigabit Ethernet XSBI is an interface standard for LANs, metropolitan
area networks (MANs), storage area networks (SANs), and WANs.
10 Gigabit Ethernet XSBI provides many features for efficient, effective
high-speed networking, including easy migration to higher performance
levels without disruption, lower cost of ownership including acquisition
and support versus other alternatives, familiar management tools and
common skills, ability to support new applications and data protocols,
flexibility in network design, and multiple vendor sourcing and
interoperability.
Under the ISO Open Systems Interconnection (OSI) model, Ethernet is a
Layer 2 protocol. 10 Gigabit Ethernet XSBI uses the IEEE 802.3 Ethernet
media access control (MAC) protocol, Ethernet frame format, and the
minimum/maximum frame size. An Ethernet PHY corresponding to OSI
layer 1 connects the media to the MAC layer that corresponds to OSI
layer 2. The PHY is divided into a physical media dependent (PMD)
element, such as optical transceivers, and a physical coding sub-layer
(PCS), which has coding and a serializer/multiplexor. This standard
defines two PHY types, including the LAN PHY and the WAN PHY,
which are distinguished by the PCS. The 10 Gigabit Ethernet XSBI
standard is a full-duplex technology standard that can increase the speed
and distance of Ethernet.
RapidIO Interconnect Specification Revision 1.1
The RapidIO interface is a communications standard used to connect
devices on a circuit board and circuit boards on a backplane. RapidIO is a
packet-switched interconnect standard designed for embedded systems
such as those used in networking and communications. The RapidIO
interface standard is a high-performance interconnect interface used for
transferring data and control information between microprocessors,
DSPs, system memory, communications and network processors, and
peripheral devices in a system.
RapidIO replaces existing peripheral bus and processor technologies
such as PCI. Some features of RapidIO include multiprocessing support,
an open standard, flexible topologies, higher bandwidth, low latency,
error management support in hardware, small silicon footprint, widely
available process and I/O technologies, and transparency to existing
applications and operating system software. The RapidIO standard
provides 10-Gbps device bandwidth using 8-bit-wide input and output
data ports. RapidIO uses LVDS technology, has the capability to be scaled
to multi-GHz frequencies, and features a 10-bit interface.
Altera Corporation
June 2006
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