EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 298
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 298 of 864
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Contents
Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices
vi
Drive Strength ...................................................................................................................................... 4–26
Hot Socketing ....................................................................................................................................... 4–27
I/O Termination .................................................................................................................................. 4–28
I/O Pad Placement Guidelines .......................................................................................................... 4–30
Power Source of Various I/O Standards ......................................................................................... 4–38
Quartus II Software Support .............................................................................................................. 4–38
Conclusion ............................................................................................................................................ 4–42
More Information ................................................................................................................................ 4–42
References ............................................................................................................................................. 4–42
Introduction ............................................................................................................................................ 5–1
Stratix I/O Banks ................................................................................................................................... 5–1
Principles of SERDES Operation ......................................................................................................... 5–6
Using SERDES to Implement DDR ................................................................................................... 5–13
Using SERDES to Implement SDR .................................................................................................... 5–14
Differential I/O Interface & Fast PLLs ............................................................................................. 5–16
Mixing Voltage Referenced & Non-Voltage Referenced Standards ....................................... 4–25
Standard Current Drive Strength ................................................................................................. 4–26
Programmable Current Drive Strength ...................................................................................... 4–27
DC Hot Socketing Specification ................................................................................................... 4–28
AC Hot Socketing Specification ................................................................................................... 4–28
Voltage-Referenced I/O Standards ............................................................................................. 4–28
Differential I/O Standards ............................................................................................................ 4–29
Differential Termination (RD) ...................................................................................................... 4–29
Transceiver Termination ............................................................................................................... 4–30
Differential Pad Placement Guidelines ....................................................................................... 4–30
VREF Pad Placement Guidelines ................................................................................................. 4–31
Output Enable Group Logic Option in Quartus II .................................................................... 4–34
Toggle Rate Logic Option in Quartus II ...................................................................................... 4–35
DC Guidelines ................................................................................................................................. 4–35
Compiler Settings ........................................................................................................................... 4–38
Device & Pin Options .................................................................................................................... 4–39
Assign Pins ...................................................................................................................................... 4–39
Programmable Drive Strength Settings ...................................................................................... 4–40
I/O Banks in the Floorplan View ................................................................................................. 4–40
Auto Placement & Verification of Selectable I/O Standards ................................................... 4–41
Stratix Differential I/O Standards ................................................................................................. 5–2
Stratix Differential I/O Pin Location ............................................................................................. 5–5
Stratix Differential I/O Receiver Operation ................................................................................. 5–7
Stratix Differential I/O Transmitter Operation ........................................................................... 5–9
Transmitter Clock Output ............................................................................................................. 5–10
Divided-Down Transmitter Clock Output ................................................................................. 5–10
Center-Aligned Transmitter Clock Output ................................................................................ 5–11
SDR Transmitter Clock Output .................................................................................................... 5–12
Clock Input & Fast PLL Output Relationship ............................................................................ 5–18
Fast PLL Specifications .................................................................................................................. 5–20
Stratix Device Handbook, Volume 2
Altera Corporation
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