EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 680
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Introduction
9–10
Stratix Device Handbook, Volume 2
TX_CLK
Data invalid window before the rising edge (T
Data invalid window after the rising edge (T
TX_CLK
Framer transmitter channel-to-channel skew
Table 9–4. SFI-4 Framer Transmitter 1 (622 MHz Clock) Mode Timing Specifications
(T
duty cycle
period
)
f
Parameter
AC Timing Specifications
Figures 9–7
characteristics of SFI-4 at the framer. Stratix and Stratix GX devices
support all the timing requirements needed to support transmitter and
receiver functions of a SFI-4 framer; only framer-related timing
specifications are applicable.
For details on the timing specifications of LVDS I/O standards in Stratix
and Stratix GX devices, see the Stratix Device Family Data Sheet section of
the Stratix Device Handbook, Volume 1 and the High-Speed Differential I/O
Interfaces in Stratix Devices chapter or the Stratix GX Device Family Data
Sheet section of the Stratix GX Device Handbook, Volume 1 and the High-
Speed Differential I/O Interfaces in Stratix Devices chapter
Figure 9–7
framer transmitter 1 (622 MHz clock) mode.
Figure 9–7. Framer Transmitter 1 (622 MHz Clock) Mode Timing Diagram
Table 9–4
1 (622 MHz clock) mode.
TX_DATA[15..0]
lists the timing specifications for the SFI-4 framer transmitter in
shows the timing diagram for the Stratix and Stratix GX
through
cq_post
cq_pre
)
T cq_pre
)
9–9
and
Min
40
Tables 9–4
T cq_post
Valid
Data
Value
1,608
Typ
through
T period
9–6
T setup
Max
200
200
200
60
illustrate the timing
Altera Corporation
T hold
July 2005
Unit
ps
ps
ps
ps
%
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