EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 606

IC STRATIX FPGA 10K LE 484-FBGA

EP1S10F484I6

Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S10F484I6

Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F484I6
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
0
Part Number:
EP1S10F484I6
0
Part Number:
EP1S10F484I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S10F484I6N
Manufacturer:
XILINX
0
Part Number:
EP1S10F484I6N
Manufacturer:
ALTERA
0
Finite Impulse Response (FIR) Filters
7–28
Stratix Device Handbook, Volume 2
time. The demultiplexer is controlled by a counter, which counts down
modulo-D starting at 0. The overall output is taken by adding the outputs
of all the filters.
The polyphase representation of the decimation filter also reduces the
computational requirement. For the example in
implementation requires 16
whereas the polyphase implementation requires only 4
computations per cycle. This saving in computational complexity is quite
significant and is often a very convincing reason to use polyphase filters.
Figure 7–16. Polyphase Filter Representation of a D=4 Decimation Filter
Decimation Using a Single Low-Pass Filter
Decimation Using a Polyphase Filter
Input
4x clock
x(n)
Input
x(n)
h(0), h(1), ... h(15)
coefficients
LPF with
Modulo 4 down
initialized at 0
counter
0
2
3
1
D = 16
h(2), h(6), h(10), h(14)
h(3), h(7), h(11), h(15)
h(0), h(4), h(8), h(12)
h(1), h(5), h(9), h(13)
with coefficients
with coefficients
with coefficients
with coefficients
Polyphase Filter
Polyphase Filter
Polyphase filter
Polyphase filter
D = 4
4 = 64 computations per cycle,
Figure
Output
y(n)
Altera Corporation
7–16, the direct
September 2004
4
1 = 16
Output
y(n)

Related parts for EP1S10F484I6