EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 319

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
clk[5..0]
pll_out[3..0]p/n
extclk4
clkloss
clkbad[1..0]
locked
activeclock
scandataout
Table 1–5. Enhanced PLL Output Signals
Port
PLL outputs driving regional or global clock
pll_out[3..0] are PLL outputs driving the four
differential or eight single-ended external clock
output pins for PLLs 5 or 6. p or n are the positive
(p) and negative (n) pins for differential pins.
PLL output driving external clock output pin from
PLLs 11 and 12
Signal indicating the switchover circuit detected a
switchover condition
Signals indicating which reference clock is no
longer toggling. clkbad1 indicates inclk1
status, clkbad0 indicates inclk0 status
Lock output from lock detect circuit active high
Signal to indicate which clock (1 = inclk0 or
0 = inclk1) is driving the PLL.
Output of the last shift register in the scan chain
Clock Multiplication & Division
Each Stratix and Stratix GX device enhanced PLL provides clock
synthesis for PLL output ports using m/(n
factors. The input clock is divided by a pre-scale counter, n, and is then
multiplied by the m feedback factor. The control loop drives the VCO to
match f
divides down the high-frequency VCO.
For multiple PLL outputs with different frequencies, the VCO is set to the
least common multiple of the output frequencies that meets its frequency
specifications. Then, the post-scale counters scale down the output
frequency for each output port. For example, if output frequencies
required from one PLL are 33 and 66 MHz, then the Quartus II software
sets the VCO to 330 MHz (the least common multiple of 33 and 66 MHz
within the VCO range).
There is one pre-scale counter, n, and one multiply counter, m, per PLL,
with a range of 1 to 512 on each. There are two post-scale counters (l) for
regional clock output ports, four counters (g) for global clock output
ports, and up to four counters (e) for external clock outputs, all ranging
from 1 to 1024 with a 50% duty cycle setting. The post-scale counters
IN
(m/n). Each output port has a unique post-scale counter that
Description
General-Purpose PLLs in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
PLL counter Internal Clock
PLL counter Pin(s)
PLL g0
counter
PLL
switchover
circuit
PLL
switchover
circuit
PLL lock
detect
PLL clock
multiplexer
PLL scan
chain
Source
post-scale counter) scaling
Pin
Logic array
Logic array
Logic array
Logic array
Logic array
Destination
1–9