EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 430
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 430 of 864
- Download datasheet (11Mb)
Stratix & Stratix GX I/O Standards
4–2
Stratix Device Handbook, Volume 2
3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) -
EIA/JEDEC Standard JESD8-B
The 3.3-V LVTTL I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVTTL standard defines the DC
interface parameters for digital circuits operating from a 3.0-V or 3.3-V
power supply and driving or being driven by LVTTL-compatible devices.
The LVTTL input standard specifies a wider input voltage range of
–0.5 V V
V. The LVTTL standard does not require input reference voltages or board
terminations.
Stratix and Stratix GX devices support both input and output levels for
3.3-V LVTTL operation.
Note to
(1)
PCI-X 1.0
AGP 1× and 2×
SSTL-3 Class I and II
SSTL-2 Class I and II
HSTL Class I
HSTL Class II
Differential HSTL
GTL
GTL+
LVDS
HyperTransport
technology
LVPECL
PCML
Differential SSTL-2
CTT
Table 4–1. I/O Standard Applications & Performance (Part 2 of 2)
These performance values are dependent on device speed grade, package type
(flip-chip or wirebond) and location of I/Os (top/bottom or left/right). See the
DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1.
I/O Standard
Table
I
3.8 V. Altera allows an input voltage range of –0.5 V V
4–1:
PC/embedded systems
Graphics processors
SDRAM
DDR I SDRAM
QDR SRAM/SRAM/CSIX
QDR SRAM/SRAM/CSIX
Clock interfaces
Backplane driver
Pentium processor interface
Communications
Motherboard interfaces
PHY interface
Communications
DDR I SDRAM
Back planes and bus interfaces 200 MHz
Application
133 MHz
66 to 133 MHz
167 MHz
160 to 400 Mbps
150 to 225 MHz
150 to 250 MHz
150 to 225 MHz
200 MHz
133 to 200 MHz
840 Mbps
800 Mbps
840 Mbps
840 Mbps
160 to 400 Mbps
Altera Corporation
Performance
Note (1)
June 2006
I
4.1
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