EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 417
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 3–10. Bidirectional DDR I/O Path in Stratix & Stratix GX Devices
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Altera Corporation
June 2006
All control signals can be inverted at the IOE. No programmable delay chains are shown in this diagram.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before input to the A
The A
This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.
The B
The tristate enable is active low by default. You can design it to be active high. The combinational control path for
the tristate is not shown in this diagram.
You can also have combinational output to the I/O pin; this path is not shown in the diagram.
Figure
OE
OE
register generates the delayed enable signal for the write strobes and write clock for memory interfaces.
register generates the enable signal for general-purpose DDR I/O applications.
3–10:
Logic Array
dataout_h
dataout_l
(4)
datain_h
outclock
combout
OE
inclock
datain_l
OE
register during compilation.
(2)
Latch C
Latch
Q
ENA
TCHLA
Output Register A
Output Register B
External Memory Interfaces in Stratix & Stratix GX Devices
OE Register B
I
D
OE Register A
DFF
DFF
DFF
DFF
D
D
D
D
neg_reg_out
Q
Q
Q
Q
OE
OE
O
O
(5)
(3)
Input Register A
Input Register B
Q
Q
DFF
DFF
0
1
D
D
0
1
I
I
Stratix Device Handbook, Volume 2
OR2
Note (1)
TRI
(6)
I/O Pin (7)
3–21
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