EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 748
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Configuration Schemes
11–30
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
f
t
t
t
t
t
t
MAX
CD2UM
CF2CD
CF2ST0
CF2ST1
STATUS
ST2CK
Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 2 of 2)
Symbol
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
This value is obtainable if users do not delay configuration by extending the nSTATUS low pulse width.
Table
DCLK
CONF_DONE
nCONFIG
nCONFIG
nCONFIG
nSTATUS
nSTATUS
11–9:
frequency
low to
low to
high to
low pulse width
high to firstrising edge of
high to user mode
CONF_DONE
nSTATUS
PPA Configuration
In PPA schemes, a microprocessor drives data to the Stratix or Stratix GX
device through a download cable. When using a PPA scheme, use a 1-k
pull-up resistor to pull the DCLK pin high to prevent unused
configuration pins from floating.
To begin configuration, the microprocessor drives nCONFIG high and
then asserts the target device’s nCS pin low and CS pin high. Next, the
microprocessor places an 8-bit configuration word on the target device’s
data inputs and pulses nWS low. On the rising edge of nWS, the target
device latches a byte of configuration data and then drives its RDYnBSY
signal low, indicating that it is processing the byte of configuration data.
The microprocessor then performs other system functions while the
Stratix or Stratix GX device is processing the byte of configuration data.
Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is high and CONF_DONE is low, the microprocessor sends the next data
byte. If nSTATUS is low, the device is signaling an error and the
microprocessor should restart configuration. However, if nSTATUS is
high and all the configuration data is received, the device is ready for
initialization. At the beginning of initialization, CONF_DONE goes high to
indicate that configuration is complete. The CONF_DONE pin must have
an external 10-k pull-up resistor in order for the device to initialize.
Initialization, by default, uses an internal oscillator, which runs at
10 MHz. After initialization, this internal oscillator is turned off. When
initialization is complete, the Stratix or Stratix GX device enters user
mode.
nSTATUS
Parameter
low
high
low
(1)
DCLK
Min
10
6
1
40
40
Max
100
800
800
20
(2)
(2)
Altera Corporation
July 2005
Units
MHz
µs
ns
ns
µs
µs
µs
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