EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 393
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
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Read-During-
Write Operation
at the Same
Address
Altera Corporation
July 2005
Power-up Conditions & Memory Initialization
Upon power-up, TriMatrix memory is in an idle state. The M512 and M4K
block outputs always power-up to zero, regardless of whether the output
registers are used or bypassed. Even if a memory initialization file is used
to pre-load the contents of the RAM block, the outputs still power-up
cleared. For example, if address 0 is pre-initialized to FF, the M512 and
M4K blocks power-up with the output at 00.
M-RAM blocks do not support memory initialization files; therefore, they
cannot be pre-loaded with data upon power-up. M-RAM blocks
combinatorial outputs and memory controls always power-up to an
unknown state. If M-RAM block outputs are registered, the registers
power-up cleared. The undefined output appears one clock cycle later.
The output remains undefined until a read operation is performed on an
address that has been written to.
The following two sections describe the functionality of the various RAM
configurations when reading from an address during a write operation at
that same address. There are two types of read-during-write operations:
same-port and mixed-port.
flow between same-port and mixed-port read-during-write.
Figure 2–14. Read-During-Write Data Flow
Same-Port Read-During-Write Mode
For read-during-write operation of a single-port RAM or the same port of
a true dual-port RAM, the new data is available on the rising edge of the
same clock cycle it was written on. This behavior is valid on all memory-
block sizes. See
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
data out
data in
Port A
Port A
Figure 2–15
Figure 2–14
for a sample functional waveform.
data out
data in
Port B
Port B
Stratix Device Handbook, Volume 2
illustrates the difference in data
Mixed-port
Same-port
data flow
data flow
2–25
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