EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 397

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Introduction
External
Memory
Standards
Altera Corporation
June 2006
S52008-3.3
f
Stratix and Stratix GX devices support a broad range of external
memory interfaces such as double data rate (DDR) SDRAM, RLDRAM II,
quad data rate (QDR) SRAM, QDRII SRAM, zero bus turnaround (ZBT)
SRAM, and single data rate (SDR) SDRAM. The dedicated phase-shift
circuitry allows the Stratix and Stratix GX devices to interface at twice the
system clock speed with an external memory (up to 200 MHz/400 Mbps).
Typical I/O architectures transmit a single data word on each positive
clock edge and are limited to the associated clock speed using this
protocol. To achieve a 400-megabits per second (Mbps) transfer rate, a
SDR system requires a 400-MHz clock. Many new applications have
introduced a DDR I/O architecture as an alternative to SDR architectures.
While SDR architectures capture data on one edge of a clock, the DDR
architectures captures data on both the rising and falling edges of the
clock, doubling the throughput for a given clock frequency and
accelerating performance. For example, a 200-MHz clock can capture a
400-Mbps data stream, enhancing system performance and simplifying
board design.
Most current memory architectures use a DDR I/O interface. These DDR
memory standards cover a broad range of applications for embedded
processor systems, image processing, storage, communications, and
networking. This chapter describes the hardware features in Stratix and
Stratix GX devices that facilitate the high-speed memory interfacing for
each memory standard. It then briefly explains how each memory
standard uses the features of the Stratix and Stratix GX devices.
You can use this document with AN 329: ZBT SRAM Controller Reference
Design for Stratix & Stratix GX Devices, AN 342: Interfacing DDR SDRAM
with Stratix & Stratix GX Devices, and AN 349: QDR SRAM Controller
Reference Design for Stratix & Stratix GX Devices.
The following sections provide an overview on using the Stratix and
Stratix GX device external memory interfacing features.
DDR SDRAM
DDR SDRAM is a memory architecture that transmits and receives data
at twice the clock speed of traditional SDR architectures. These devices
transfer data on both the rising and falling edge of the clock signal.
Interfaces in Stratix &
3. External Memory
Stratix GX Devices
3–1