EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 461
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484I6
Manufacturer Part Number
EP1S10F484I6
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S10F484I6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484I6
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
June 2006
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA
Thermally enhanced FineLine BGA and
thermally enhanced BGA cavity up
Non-thermally enhanced cavity up and
non-thermally enhanced FineLine BGA
Table 4–9. Bidirectional pad Limitation Formulas (Where VREF Inputs Exist)
Table 4–10. Bidirectional Pad Limitation Formulas (Where VREF Outputs Exist)
Package Type
Package Type
The previous equation accounts for the input limitations, but you must
apply the appropriate equation from
limitations.
When at least one additional output exists but no voltage referenced
inputs exist, apply the appropriate formula from
When additional voltage referenced inputs and other outputs exist in the
same VREF bank, then the bidirectional pad limitation must again
simultaneously adhere to the input and output limitations. See the
following equation.
<Total number of bidirectional pads> + <Total number of input pads> 40 (20 on
each side of the VREF pad)
<Total number of bidirectional pads> 20 (per
<Total number of bidirectional pads> 15 (per
<Total number of bidirectional pads> + <Total number of additional
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> 20 (per
<Total number of bidirectional pads> + <Total number of additional
output pads> – <Total number of pads from the smallest group of pads
controlled by an OE> 15 (per
Selectable I/O Standards in Stratix & Stratix GX Devices
Formula
Formula
VREF
VREF
Table 4–9
Stratix Device Handbook, Volume 2
pad)
pad)
to determine the output
Table
VREF
VREF
4–10.
pad)
pad)
4–33
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