EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 719

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Introduction
Altera Corporation
July 2005
Fast passive parallel (FPP)
Passive serial (PS)
Passive parallel
asynchronous (PPA)
Remote/local update FPP
Remote/local update PS
Remote/local update PPA
Joint Test Action Group
(JTAG)
S52013-3.2
Table 11–1. Stratix & Stratix GX Device Configuration Schemes
Configuration Scheme
You can configure Stratix and Stratix GX devices using one of several
configuration schemes. All configuration schemes use either a
microprocessor, configuration device, or a download cable. See
Table
This chapter discusses how to configure one or more Stratix or Stratix GX
devices. It should be used together with the following documents:
■
■
■
■
■
■
Configuration with a parallel synchronous configuration device or microprocessor
interface where eight bits of configuration data are loaded on every clock cycle.
Configuration with a serial synchronous microprocessor interface or the
MasterBlaster
ByteBlasterMV parallel port download cable.
Configuration with a parallel asynchronous microprocessor interface. In this
scheme, the microprocessor treats the target device as memory.
Configuration using a Nios
embedded processor. Allows you to update the Stratix or Stratix GX device
configuration remotely using the FPP scheme to load data.
Passive serial synchronous configuration using a Nios or other embedded
processor. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PS scheme to load data.
Passive parallel asynchronous configuration using a Nios or other embedded
processor. In this scheme, the Nios microprocessor treats the target device as
memory. Allows you to update the Stratix or Stratix GX device configuration
remotely using the PPA scheme to load data.
Configuration through the IEEE Std. 1149.1 JTAG pins. You can perform JTAG
configuration with either a download cable or an embedded device. Ability to use
SignalTap
MasterBlaster Serial/USB Communications Cable Data Sheet
USB Blaster USB Port Download Cable Development Tools Data Sheet
ByteBlaster II Parallel Port Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheets
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet
11–1.
®
II Embedded Logic Analyzer.
TM
communications cable, USB Blaster, ByteBlaster
TM
11. Configuring Stratix &
(16-bit ISA) and Nios
Typical Use
Stratix GX Devices
®
II (32-bit ISA) or other
TM
II, or
11–1