EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 318

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Enhanced PLLs
1–8
Stratix Device Handbook, Volume 2
inclk[1..0]
fbin
pllena
clkswitch
areset
clkena[5..0]
extclkena[3..0]
pfdena
scanclk
scandata
scanaclr
Table 1–4. Enhanced PLL Input Signals
Port
Primary and secondary reference clock inputs to
PLL
External feedback input to the PLL (PLLs 5 and 6
only)
Enable pin for enabling or disabling all or a set of
PLLs active high
Switchover signal used to initiate external clock
switchover control this signal switches the clock
on the rising edge of clkswitch
Signal used to reset the PLL which re-
synchronizes all the counter outputs active high
Enable clock driving regional or global
clock active high
Enable clock driving external clock (PLLs 5 and 6
only) active high
Enables the outputs from the phase frequency
detector active high
Serial clock signal for the real-time PLL control
feature
Serial input data stream for the real-time PLL
control feature
Serial shift register reset clearing all registers in
the serial shift chain active high
Tables 1–4
and
Description
1–5
describe all the enhanced PLL ports.
Pin
Pin
Pin
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Source
Altera Corporation
×n counter
Phase frequency
detector (PFD)
General PLL
control signal
PLL switchover
circuit
General PLL
control signal
Clock output
Clock output
PFD
Reconfiguration
circuit
Reconfiguration
circuit
Reconfiguration
circuit
Destination
July 2005