ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet
ADUC7033BCPZ-8L-RL
Specifications of ADUC7033BCPZ-8L-RL
Related parts for ADUC7033BCPZ-8L-RL
ADUC7033BCPZ-8L-RL Summary of contents
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FEATURES High precision ADCs Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs Programmable ADC throughput from kHz On-chip 5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain from 1 to 512 ADC input range: ...
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ADuC7033 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Electrical Specifications ............................................................... 4 Timing Specifications ................................................................ 10 Absolute Maximum Ratings .......................................................... 15 ESD Caution ................................................................................ 15 Pin ...
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REVISION HISTORY 10/10—Rev Rev. B Changes to Table 32 ........................................................................ 47 Changes to Timers Section ............................................................ 74 Added Synchronization of Timers across Asynchronous Clock Domains Section, Figure 32, and Figure 33 ................................. 74 Added Programming the Timers Section ...
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ADuC7033 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3 VREF = 1.2 V internal reference, f precision oscillator, all specifications T A Table 1. ADuC7033 Electrical Specifications Parameter Test Conditions/Comments ADC SPECIFICATIONS Conversion Rate 1 Chop off, ADC ...
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Parameter Test Conditions/Comments 13, 14 Total Gain Error Includes resistor mismatch Temperature range = −25°C to +65°C Gain Drift Includes resistor mismatch drift 1, 10, 15 Output Noise 4 Hz update rate, chop enabled 10 Hz update ...
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ADuC7033 Parameter Test Conditions/Comments ADC Low Power Reference Internal V REF Initial Accuracy Measured Initial Accuracy Using ADCREF, measured Temperature Coefficient RESISTIVE ATTENUATOR Divider Ratio Resistor Mismatch Drift ADC GROUND SWITCH Resistance Direct ...
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Parameter Test Conditions/Comments MCU START-UP TIME At Power-On Includes kernel power-on execution time After Reset Event Includes kernel power-on execution time From MCU Power-Down Oscillator Running Wake Up from Interrupt Wake Up from LIN Crystal Powered Down Wake Up from ...
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ADuC7033 Parameter Test Conditions/Comments D2 Duty Cycle SUP BSD INPUT/OUTPUT Baud Rate Input Leakage Current Input (high) = VDD or input (low) = IO_VSS V , Output Low Voltage ...
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Not guaranteed by production test, but by design and/or characterization data at production release. 2 Valid for current ADC gain setting of PGA = 4 to 64. 3 These numbers include temperature drift. 4 Tested at gain range = ...
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ADuC7033 TIMING SPECIFICATIONS SPI Timing Specifications Table 2. SPI Master Mode Timing (PHASE Mode = 1) Parameter Description 1 t SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV ...
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Table 3. SPI Master Mode Timing (PHASE Mode = 0) Parameter Description 1 t SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK ...
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ADuC7033 Table 4. SPI Slave Mode Timing (PHASE Mode = 1) Parameter Description SS to SCLK edge SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge ...
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Table 5. SPI Slave Mode Timing (PHASE Mode = 0) Parameter Description SS to SCLK edge SCLK low pulse width SL t SCLK high pulse width Data output valid after SCLK edge DAV ...
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ADuC7033 LIN Timing Specifications RECESSIVE TRANSMIT INPUT TO TRANSMITTING NODE DOMINANT TH REC (MAX) TH DOM (MAX) V SUP (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) TH REC (MIN) TH DOM (MIN) RxD (OUTPUT OF RECEIVING NODE 1) RxD (OUTPUT OF RECEIVING ...
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ABSOLUTE MAXIMUM RATINGS T = −40°C to +115°C, unless otherwise noted. A Table 6. Parameter Rating AGND to DGND to VSS to IO_VSS −0 +0.3 V VBAT to AGND − +40 V VDD to VSS −0.3 ...
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ADuC7033 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET GPIO_5/IRQ1/RxD GPIO_6/TxD GPIO_7/IRQ4 GPIO_8/IRQ5 NTRST Table 7. Pin Function Descriptions Pin No. Mnemonic Type 1 RESET I 2 GPIO_5/IRQ1/RxD I/O 3 GPIO_6/TxD I/O 4 GPIO_7/IRQ4 I/O 5 GPIO_8/IRQ5 I/O 6 TCK I 1 ...
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Pin No. Mnemonic Type 7 TDI I 8, 34, 35 DGND S 9, 16, 17, NC 23, 25, 26, 32 40, 43 TDO O 11 NTRST I 12 TMS I 13 VBAT I 14 VREF I ...
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ADuC7033 Pin No. Mnemonic Type 31 GPIO_4/ECLK I/O 33 REG_DVDD S 36 XTAL1 O 37 XTAL2 I/O 42 VDD S 44 VSS S 46 STI I/O 47 IO_VSS S 48 LIN/BSD I input, O ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –0.5 VDD = 4V –1.0 –1.5 –2.0 VDD = 18V –2.5 –3.0 –3.5 – TEMPERATURE (°C) Figure 8. ADC Current Channel Offset vs. Temperature, 10 MHz MCU 0 –0.5 –1.0 –40°C –1.5 +25°C –2.0 ...
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ADuC7033 TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, after the ADC settles. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that while the ADC front-end signal ...
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THEORY OF OPERATION The ADuC7033 is a complete system solution for battery monitoring automotive applications. The device integrates all of the required features to precisely and intelli- gently monitor, process, and diagnose 12 V battery parameters, including ...
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ADuC7033 • Normal interrupt (IRQ). This is provided to service general-purpose interrupt handling of internal and external events. • Fast interrupt (FIQ). This is provided to service data transfer or a communication channel with low latency. FIQ has priority over ...
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MEMORY ORGANIZATION The ARM7, a von Neumann architecture, MCU core sees 32 memory as a linear array of 2 byte locations. As shown in Figure 13, the ADuC7033 maps this into four distinct user areas, namely: a memory area that ...
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ADuC7033 Remap Operation When a reset occurs on the ADuC7033, execution starts automatically in the factory programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC7033 is in normal mode, it ...
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RESET There are four kinds of reset: external reset, power-on-reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. The ...
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ADuC7033 FLASH/EE MEMORY The ADuC7033 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit repro- grammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, the ...
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User software must ensure that the Flash/EE memory controller has completed any erase or write cycle before the PLL is powered down. If the PLL is powered down before an erase or FEE0CON and FEE1CON Registers Name: FEE0CON and FEE1CON ...
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ADuC7033 Command Sequence for Executing a Mass Erase Giving the significance of the mass erase command, a specific code sequence must be executed to initiate this operation. 1. Set Bit 3 in FEExMOD. 2. Write 0xFFC3 in FEExADR 3. Write ...
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FEE0ADR and FEE1ADR Registers Name: FEE0ADR and FEE1ADR Address: 0xFFFF0E10 and 0xFFFF0E90 Default 0x0000 (FEE1ADR). For FEE0ADR, see the Value: System Identification FEE0ADR section. Access: Read/write Function: This 16-bit register dictates the address upon which any Flash/EE command executed via ...
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ADuC7033 FLASH/EE MEMORY SECURITY The Flash/EE memory available to the user can be read and write protected using the FFE0HID and FEE1HID registers. In Block0, the FEE0HID MMR protects the Flash/EE memory. Bit 0 ...
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Block1, Flash/EE Memory Protection Registers Name: FEE1HID and FEE1PRO Address: 0xFFFF0EA0 (for FEE1HID) and 0xFFFF0E9C (for FEE1PRO) Default Value: 0xFFFFFFFF (for FEE1HID) and 0x00000000 (for FEE1PRO) Access: Read/write access Function: These registers are written by user code to configure the ...
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ADuC7033 In summary, there are three levels of protection. Temporary Protection Set and remove temporary protection by writing directly into the FEExHID MMR. This register is volatile and therefore protection is only in place while the part remains powered on. ...
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FLASH/EE MEMORY RELIABILITY The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through ...
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ADuC7033 ADuC7033 KERNEL The ADuC7033 features an on-chip kernel resident in the top the Flash/EE code space. After any reset event, this kernel copies the factory calibrated data from the manufacturing data space into the various on-chip ...
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INITIALIZE ON-CHIP PERIPHERALS TO FACTORY CALIBRATED STATE NO JTAG MODE? NTRST = 1 NO PAGE ERASED? KEY PRESENT? 0x14 = 0xFFFFFFFF 0x14 = 0x27011970 YES CHECKSUM PRESENT? 0x14 = CHECKSUM FLAG PAGE 0 ERROR NO YES RESET LIN COMMAND COMMAND ...
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ADuC7033 MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the top the MCU memory space and accessed by indirect addressing, load, and store commands through the ARM7 banked registers. An outline of the ...
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COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write. Table 19. IRQ Address Base = 0xFFFF0000 Access Address Name Byte ...
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ADuC7033 Access Address Name Byte Type 0x0340 T2LD 4 RW 0x0344 T2VAL 4 R 0x0348 T2CON 2 RW 0x034C T2CLRI 1 W 0x0360 T3LD 2 RW 0x0364 T3VAL 2 R 0x0368 T3CON 0x036C T3CLRI 1 W 0x0380 ...
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Table 23. ADC Address Base = 0xFFFF0500 Access Address Name Byte Type 0x0500 ADCSTA 2 R 0x0504 ADCMSKI 1 RW 0x0508 ADCMDE 1 RW 0x050C ADC0CON 2 RW 0x0510 ADC1CON 2 RW 0x0518 ADCFLT 2 RW 0x051C ADCCFG 1 RW ...
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ADuC7033 Table 24. UART Base Address = 0xFFFF0700 Address Name Byte Access Type 0x0700 COMTX 1 W 0x0700 COMRX 1 R 0x0700 COMDIV0 1 RW 0x0704 COMIEN0 1 RW 0x0704 COMDIV1 1 RW 0x0708 COMIID0 1 R 0x070C COMCON0 1 ...
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Table 27. STI Base Address = 0xFFFF0880 Access Address Name Byte Type 0x0880 STIKEY0 4 W 0x0884 STICON 2 RW 0x0888 STIKEY1 4 W 0x088C STIDAT0 2 RW 0x0890 STIDAT1 2 RW 0x0894 STIDAT2 2 RW Table 28. SPI Base ...
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ADuC7033 Table 30. Flash/EE Base Address = 0xFFFF0E00 Access Address Name Byte Type 0x0E00 FEE0STA 1 R 0x0E04 FEE0MOD 1 RW 0x0E08 FEE0CON 1 RW 0x0E0C FEE0DAT 2 RW 0x0E10 FEE0ADR 2 RW 0x0E18 FEE0SIG 3 R 0x0E1C FEE0PRO 4 ...
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ANALOG-TO-DIGITAL CONVERTERS The ADuC7033 incorporates two independent sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), namely: the current channel ADC (I-ADC) and the voltage/temperature channel ADC (V/T-ADC). These precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit, Σ-Δ modulators, ...
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ADuC7033 Figure 17. Current ADC, Top Level Overview Rev Page 44 of 140 ...
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VOLTAGE/TEMPERATURE CHANNEL ADC (V/T-ADC) The voltage/temperature channel ADC (V/T-ADC) converts additional battery parameters such as voltage and temperature. The input to this channel can be multiplexed from one of three input sources, namely: an external voltage, an external tempera- ture ...
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ADuC7033 ADC GROUND SWITCH The ADuC7033 features an integrated ground switch pin, GND_SW, Pin15. This switch allows the user to dynamically disconnect ground from external devices. It allows either a direct connection to ground connection to ground using ...
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ADC NOISE PERFORMANCE TABLES Table 32, Table 33, and Table 34 list the output rms noise in μV for some typical output update rates on the I- and V/T-ADCs. The numbers are typical and are generated at a differential input ...
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ADuC7033 ADC MMR INTERFACE The ADC is controlled and configured through a number of MMRs described in detail in the following sections. All bits defined in the top eight MSBs (Bits[15:8]) of the MMR are used as flags only and ...
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Bit Description 2 Temperature Conversion Result Ready Bit. If the temperature channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in the temperature data register (ADC2DAT MMR ...
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ADuC7033 ADC Mode Register Name: ADCMDE Address: 0xFFFF0508 Default Value: 0x00 Access: Read/write Function: The ADC Mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 36. ADCMDE MMR Bit Designations Bit Description ...
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Current Channel ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default Value: 0x0000 Access: Read/write Function: The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC. Note: If the current ADC is reconfigured via ...
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ADuC7033 Voltage/Temperature Channel ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default Value: 0x0000 Access: Read/write Function: The voltage/temperature channel ADC control MMR is a 16-bit register that is used to configure the V/T-ADC. Note: When enabling/disabling the voltage/temperature ADC, the ...
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ADC Filter Register Name: ADCFLT Address: 0xFFFF0518 Default Value: 0x0007 Access: Read/write Function: The ADC Filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs. Note: If ADCFLT is modified, the current and voltage/temperature ...
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ADuC7033 Table 40. ADC Conversion Rates and Settling Times Chop Enabled Averaging Factor Yes No Yes Yes N additional time of approximately 60 μs per ADC is required before the first ADC is ...
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ADC Configuration Register Name: ADCCFG Address: 0xFFFF051C Default Value: 0x00 Access: Read/write Function: The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs. Table 42. ADCCFG MMR Bit Designations Bit Description 7 Analog Ground Switch Enable. Set ...
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ADuC7033 Current Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF0520 Default 0x0000 Value: Access: Read only Function: This ADC Data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC0 conversion ...
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Temperature Channel ADC Offset Calibration Register Name: ADC2OF Address: 0xFFFF0538 Default Part specific, factory programmed Value: Access: Read/write Function: This ADC Offset MMR holds a 16-bit offset cali- bration coefficient for the temperature channel. The register is configured at power-on ...
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ADuC7033 Current Channel ADC Result Counter Limit Register Name: ADC0RCL Address: 0xFFFF0548 Default 0x0001 Value: Access: Read/write Function: This 16-bit MMR sets the number of conversions required before an ADC interrupt is generated. By default this register is set to ...
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Low Power Voltage Reference Scaling Factor Name: ADCREF Address: 0xFFFF057C Default Part specific, factory programmed Value: Access: Read/write. This register should not be used if the precision reference is being used in low power mode (if ADCMDE[5] is set). Function: ...
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ADuC7033 ADC Comparator and Accumulator Every I-ADC result can also be compared to a preset threshold level (ADC0TH) as configured via ADCCFG[4:3]. An MCU interrupt is generated if the absolute (sign independent) value of the ADC result is greater than ...
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FREQUENCY (kHz) Figure 23. Typical Digital Filter Response at f ADC A modified version of the 8 kHz filter response can ...
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ADuC7033 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (kHz) Figure 27. Typical Digital Filter Response at f ADC In general possible to program different values of ...
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Self-Calibration In self (offset or gain) calibration, the ADC generates its calibration coefficient based on an internally generated the case of self-offset calibration, and full-scale voltage in the case of self-gain calibration. It should be emphasized that ...
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ADuC7033 In summary, the simplified ADC transfer function can be described as ⎡ × V PGA = − IN ADC ⎢ ADCOF OUT V ⎣ REF This equation is valid for the voltage/temperature channel ADC. For the current channel ADC, ...
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POWER SUPPLY SUPPORT CIRCUITS The ADuC7033 incorporates two on-chip, low dropout (LDO) regulators that are driven directly from the battery voltage to generate a 2.6 V internal supply. This 2.6 V supply is then used as the supply voltage for ...
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ADuC7033 SYSTEM CLOCKS The ADuC7033 integrates a very flexible clocking system that can be clocked from one of three sources: an integrated on-chip precision oscillator, an integrated on-chip low power oscillator external watch crystal. These three options are ...
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The operating mode, clocking mode, and programmable clock divider are controlled using two MMRs, PLLCON and POWCON, and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clock system and POWCON controls both ...
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ADuC7033 PLLCON Prewrite Key PLLKEY0 Name: PLLKEY0 Address: 0xFFFF0410 Access: Write only Key: 0x000000AA Function: PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLKEY0 is the prewrite key. PLLCON Postwrite ...
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Table 46. POWCON MMR Bit Designations Bit Description Reserved. 7 Precision 131 kHz Input Enable. Cleared by the user to power-down the precision 131 kHz input enable. Set by the user to enable the precision 131 kHz ...
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ADuC7033 User code then reads back the value of the low power oscillator calibration counter. There are three possible scenarios: • OSC0VAL0 = OSC0VAL1. No further action is required. • OSC0VAL0 > OSC0VAL1. The low power oscillator is running slow. ...
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OSC0STA Register Name: OSC0STA Address: 0xFFFF0444 Default 0x00 Value: Access: Read access only Function: This 8-bit register gives the status of the low power oscillator calibration routine. Table 49. OSC0STA MMR Bit Designations Bit Description Reserved. 1 ...
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ADuC7033 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 17 interrupt sources on the ADuC7033 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals such as the ADC, UART, and so on. The ARM7TDMI CPU ...
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IRQ The IRQ is the exception signal to enter the IRQ mode of the processor used to service general-purpose interrupt handling of internal and external events. All 32 bits are logically OR’ create a single ...
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ADuC7033 TIMERS The ADuC7033 features five general-purpose timer/counters. • Timer0, or lifetime timer • Timer1 • Timer2 or wake-up timer • Timer3 or watchdog timer • Timer4 or STI timer The five timers in their normal mode of operation can ...
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ARM7TDMI AMBA CORE CLOCK LOW POWER OSCILLATOR GPIO HIGH PRECISION OSCILLATOR XTAL CORE CLOCK (F ) CORE DOMAIN As shown in Figure 32, the MMR logic and core timer logic reside in separate and asynchronous clock domains. Any data coming ...
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ADuC7033 Starting Timer2 When starting Timer2 recommended to first load Timer2 with the required TxLD value. Next, start the timer by setting the T2CON bits as required. This enables the timer but only once the T2CON bits have ...
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TIMER0—LIFETIME TIMER Timer0 is a general-purpose, 48-bit count up 16-bit count up/down timer with a programmable prescaler. Timer0 can be clocked from either the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, ...
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ADuC7033 Timer0 Control Register Name: T0CON Address: 0xFFFF030C Default Value: 0x00000000 Access: Read/write Function: The 32-bit MMR configures the mode of operation for Timer0. Table 53. T0CON MMR Bit Designations Bit Description Reserved. 17 Event Select Bit. ...
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Timer0 Load Registers Name: T0LD Address: 0xFFFF0300 Default 0x0000 Value: Access: Read/write Function: T0LD0 is the 16-bit register holding the 16-bit value that is loaded into the counter. Available in 16-bit mode only. Timer0 Clear Register Name: T0CLRI Address: 0xFFFF0310 ...
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ADuC7033 TIMER1 Timer1 is a 32-bit general-purpose timer, count-down or count- up, with a programmable prescaler. The prescaler source can be the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source can ...
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Timer1 Capture Register Name: T1CAP Address: 0xFFFF0330 Default Value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Timer1 Control Register Name: T1CON Address: 0xFFFF0328 Default Value: 0x01000000 Access: Read/write Function: ...
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ADuC7033 Bit Description Format binary (default reserved hours:minutes:seconds:hundredths (23 hours to 0 hours hours:minutes:seconds:hundredths (255 hours to 0 hours Prescaler. 0000 = source clock/1 (default). 0100 ...
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Timer2 Control Register Name: T2CON Address: 0xFFFF0348 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the mode of operation of Timer2. Table 55. T2CON MMR Bit Designations Bit Description Reserved Clock Source ...
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ADuC7033 TIMER3 OR WATCHDOG TIMER LOW POWER 32.768kHz Timer3 has two modes of operation, normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. When enabled, it requires periodic servicing to prevent it ...
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Timer3 Control Register Name: T3CON Address: 0xFFFF0368 Default Value: 0x0000 Access: Read/write Function: The 16-bit MMR configures the mode of operation of Timer3 as described in detail in Table 56. Table 56. T3CON MMR Bit Designations Bit Description 15 to ...
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ADuC7033 TIMER4 OR STI TIMER Timer4 is a general-purpose, 16-bit, count up/count down timer with a programmable prescaler. Timer4 can be clocked from the core clock or the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, ...
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Table 57. T4CON MMR Bit Designations Bit Description Reserved. 17 Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event Event ...
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ADuC7033 GENERAL-PURPOSE INPUT/OUTPUT The ADuC7033 features nine general-purpose bidirectional input/output (GPIO) pins. In general, many of the GPIO pins have multiple functions that can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All ...
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Table 58. External GPIO Pin to Internal Port Signal Assignments Port GPIO Pin Port Signal Port0 GPIO_0 P0.0 IRQ0 SS GPIO_1 P0.1 SCLK GPIO_2 P0.2 MISO GPIO_3 P0.3 MOSI GPIO_4 P0.4 ECLK 1 P0.5 1 P0.6 Port1 GPIO_5 P1.0 IRQ1 ...
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ADuC7033 GPIO Port0 Control Register Name: GP0CON Address: 0xFFFF0D00 Default Value: 0x11100000 Access: Read/write Function: The 32-bit MMR selects the pin function for each Port0 pin. Table 59. GP0CON MMR Bit Designations Bit Description Reserved. These bits ...
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GPIO Port1 Control Register Name: GP1CON Address: 0xFFFF0D04 Default Value: 0x10000000 Access: Read/write Function: The 32-bit MMR selects the pin function for each Port1 pin. Table 60. GP1CON MMR Bit Designations Bit Description Reserved. These bits are ...
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ADuC7033 Bit Description 4 GPIO_8 Function Select Bit. Cleared by user code configure the GPIO_8 pin as a general-purpose I/O (GPIO) pin. Set by user code route the LIN/BSD input data to the GPIO_8 ...
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GPIO Port0 Data Register Name: GP0DAT Address: 0xFFFF0D20 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 58). This register also sets the output value for GPIO pins ...
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ADuC7033 GPIO Port1 Data Register Name: GP1DAT Address: 0xFFFF0D30 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 58). This register also sets the output value for GPIO ...
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GPIO Port2 Data Register Name: GP2DAT Address: 0xFFFF0D40 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 58). This register also sets the output value for GPIO pins ...
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ADuC7033 GPIO Port0 Set Register Name: GP0SET Address: 0xFFFF0D24 Access: Write only Function: This 32-bit MMR allows user code to individually bit address external GPIO pins to set them high only. User code can accomplish this using the GP0SET MMR ...
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GPIO Port2 Set Register Name: GP2SET Address: 0xFFFF0D44 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this using the GP2SET MMR without having ...
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ADuC7033 GPIO Port1 Clear Register Name: GP1CLR Address: 0xFFFF0D38 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish this using the GP1CLR MMR without ...
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HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7033 integrates a number of high voltage circuit functions that are controlled and monitored through a regis- tered interface consisting of two MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command ...
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ADuC7033 High Voltage Interface Control Register Name: HVCON Address: 0xFFFF0804 Default Value: Updated by kernel Access: Read/write Function: This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this register are interpreted ...
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High Voltage Data Register Name: HVDAT Address: 0xFFFF080C Default Value: Updated by kernel Access: Read/write Function: HVDAT is a 12-bit register that is used to hold data to be written indirectly to, and read indirectly from, the following high voltage ...
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ADuC7033 High Voltage Configuration0 Register Name: HVCFG0 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7033. This register is not an ...
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High Voltage Configuration1 Register Name: HVCFG1 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7033. This register is not an MMR ...
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ADuC7033 High Voltage Monitor Register Name: HVMON Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only Function: This 8-bit, read only register reflects the current status of enabled high voltage related circuits and functions ...
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High Voltage Status Register Name: HVSTA Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only, this register should only be read on a high voltage interrupt Function: This 8-bit, read-only register reflects a change ...
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ADuC7033 WAKE-UP (WU) PIN The wake-up (WU) pin is a high voltage GPIO controlled through HVCON and HVDAT. WU Pin Circuit Description The WU pin is configured by default as an output with an internal 10 kΩ pull-down resistor and ...
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HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE An interrupt controller is also integrated with the high voltage circuits. If enabled through IRQEN[16], one of six high voltage sources can assert the high voltage interrupt (IRQ3) signal and interrupt ...
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ADuC7033 UART SERIAL INTERFACE The ADuC7033 features a 16,450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial conver- sion on data characters received from ...
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UART Tx Register Name: COMTX Address: 0xFFFF0700 Access: Write only Function: Write to this 8-bit register to transmit data using the UART. UART Rx Register Name: COMRX Address: 0xFFFF0700 Default 0x00 Value: Access: Read only Function: This 8-bit register is ...
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ADuC7033 UART Control Register 0 Name: COMCON0 Address: 0xFFFF070C Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the operation of the UART in conjunction with COMCON1. Table 81. COMCON0 MMR Bit Designations Bit Name 7 DLAB 6 BRK ...
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UART Control Register 1 Name: COMCON1 Address: 0xFFFF0710 Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0. Table 82. COMCON1 MMR Bit Designations Bit Name ...
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ADuC7033 UART Interrupt Enable Register 0 Name: COMIEN0 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: The 8-bit register enables and disables the individual UART interrupt sources. Table 84. COMIEN0 MMR Bit Designations Bit Name EDSSI ...
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UART Fractional Divider Register Name: COMDIV2 Address: 0xFFFF072C Default Value: 0x0000 Access: Read/write Function: This 16-bit register controls the operation of the fractional divider for the ADuC7033. Table 86. COMDIV2 MMR Bit Designations Bit Name 15 FBEN ...
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ADuC7033 SERIAL PERIPHERAL INTERFACE The ADuC7033 features a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. ...
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SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: The 16-bit MMR configures the serial peripheral interface. Table 89. SPICON MMR Bit Designations Bit Description Reserved. 12 Continuous Transfer Enable. Set by the ...
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ADuC7033 SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default 0x00 Value: Access: Read only Function: The 8-bit MMR represents the current status of the serial peripheral interface. Table 90. SPISTA MMR Bit Designations Bit Description Reserved. 5 ...
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SERIAL TEST INTERFACE The ADuC7033 incorporates single pin, serial test interface (STI) ports that can be used for end-customer evaluation or diagnostics on finished production units. The STI port transmits from one byte to six bytes of data in 12-bit ...
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ADuC7033 Serial Test Interface Data 2 Register Name: STIDAT1 Address: 0xFFFF0894 Default 0x0000 Value: Access: Read/write Function: The STIDAT2 MMR is a 16-bit register that holds the fifth and sixth data bytes that are to be trans- mitted on the ...
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Table 91. STICON MMR Bit Designations Bit Description Reserved. These bits are reserved for future use and should be written user code State Bits, Read Only. If the interface is in ...
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ADuC7033 An example code segment configuring the STI port to transmit five bytes and then to transmit two bytes follows: T4LD = 267; T4CON = 0xC0; STIKEY0 = 07; STICON = 0x11; STIKEY1 = 0xb9; STIDAT0 = 0xAABB; STIDAT1 = ...
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LIN (LOCAL INTERCONNECT NETWORK) INTERFACE The ADuC7033 features high voltage physical interfaces between the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1 kBaud to 20 kBaud, and it ...
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ADuC7033 LIN Hardware Synchronization Status Register Name: LHSSTA Address: 0xFFFF0780 Default Value: 0x00 Access: Read only Function: The LHS status register is a 32-bit register whose bits reflect the current operating status of the ADuC7033 LIN interface. Table 93. LHSSTA ...
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LIN Hardware Synchronization Control Register 0 Name: LHSCON0 Address: 0xFFFF0784 Default Value: 0x0000 Access: Read/write Function: The LHS control register is a 32-bit register that, in conjunction with the LHSCON1 register, is used to configure the LIN mode of operation. ...
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ADuC7033 Bit Description 7 Sync Timer Stop Edge Type Bit. Cleared user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4] register. Set user code to stop the ...
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LIN Hardware Synchronization Control Register 1 Name: LHSCON1 Address: 0xFFFF078C Default Value: 0x32 Access: Read/write Function: The LHS control register is a 32-bit register that, in conjunction with the LHSCON0 register, is used to configure the LIN mode of operation. ...
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ADuC7033 LIN HARDWARE INTERFACE LIN Frame Protocol The LIN frame protocol is broken into four main categories: break symbol, sync byte, protected identifier, and data bytes. The format of the frame header, break, synchronization byte, and protected identifier are shown ...
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BIT BIT 13T > BIT BIT BIT BIT BIT STA BREAK SYNC Figure 46. LIN Interface Timing T > 13T BREAK BIT START BIT Figure 47. LIN Break ...
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ADuC7033 Example LIN Hardware Synchronization Routine Consider the following C-Source Code LIN initialization routine. void LIN_INIT(void ) { char HVstatus; GPCON = 0x110000; LHSCON0 = 0x1; do{ HVDAT = 0x02; HVCON = 0x08; do{ HVstatus = HVCON; } while(HVstatus & ...
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LHSCON0 = 0x4; IRQEN = 0x800; LHSVAL1 BREAK LHSVAL0 STARTS RESET AND COMPARE COUNTING STARTS INTERRUPT COUNTING GENERATED T START BIT LHSVAL1 = 0x3F LIN Diagnostics The ADuC7033 features the capability to ...
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ADuC7033 BIT SERIAL DEVICE (BSD) INTERFACE LHS INTERRUPT IRQEN[7] ADuC7033 LHS HARDWARE 5MHz LHSVAL0 131kHz LHSVAL1 RxD ENABLE LHSCON0[8] ADuC7033 UART BSD is a pulse-width modulated signal with three possible states: sync, zero, and one. These are detailed, together with ...
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Detailed bit definitions for most of these MMRs have been listed previously. In addition to the registers described in the LIN MMR Description section, LHSCAP and LHSCMP are registers that are required for the operation of the BSD interface. Details ...
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ADuC7033 BUS RELEASED BY BUS PULLED LOW SLAVE AFTER BY MASTER BUS HELD LOW t BY SLAVE SYNC RELEASED BY t MASTER 0 Figure 55. BSD Slave Transmitting Zero Typical BSD Program Flow Because BSD is a PWM communications protocol ...
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LHSVAL0 LOADED LHSCMP = LHSVAL0 2 4 INTO LHSCAP HERE INTERRUPT GENERATED HERE SOFTWARE DEASSERTS 5 BSD HIGH HERE MASTER DRIVES SOFTWARE ASSERTS 1 3 BSD LOW HERE BSD BUS LOW BSD ‘0’ PERIOD BSD ‘1’ PERIOD Figure 58. Master ...
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ADuC7033 PART IDENTIFICATION Two registers mapped into the MMR space are intended to allow user code to identify and trace manufacturing lot ID information, part ID number, silicon mask revision, and kernel revision. This information is contained in the SYSSER0 ...
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System Serial ID Register 1 Name: SYSSER1 Address: 0xFFFF023C Default Value: 0x00000000 (updated by kernel at power-on) Access: Read/write Function: At power-on, this 32-bit register holds the values of the part ID number, silicon mask revision number, and kernel revision ...
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ADuC7033 System Identification FEE0ADR Name: FEE0ADR Address: 0xFFFF0E10 Default Value: Nonzero Access: Read/write Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEE0CON acts. Note: This MMR is also used to identify the ADuC703x family ...
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SCHEMATIC This example schematic represents a basic functional circuit implementation. Additional components need to be added to ensure that the system meets any EMC and other overvoltage/overcurrent compliance requirements. Figure 59. Schematic Rev Page 137 of 140 ADuC7033 ...
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ADuC7033 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1 Model Temperature Range ADuC7033BSTZ-88 −40°C to +115°C ADuC7033BSTZ-88-RL −40°C to +115° RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 ...
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NOTES Rev Page 139 of 140 ADuC7033 ...
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ADuC7033 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06847-0-10/10(B) Rev Page 140 of 140 ...