ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 122

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
LIN Hardware Synchronization Status Register
Name:
Address:
Default Value:
Access:
Function:
Table 93. LHSSTA MMR Bit Designations
Bit
31 to 7
6
5
4
3
2
1
0
LHSSTA
0xFFFF0780
0x00
Read only
The LHS status register is a 32-bit register whose bits reflect the current operating status of the ADuC7033 LIN
interface.
Description
Reserved. These read-only bits are reserved for future use.
Rising Edge Detected (BSD Mode Only).
Set to 1 by hardware to indicate a rising edge has been detected on the BSD bus.
Cleared to 0, after user code reads the LHSSTA MMR.
LHS Reset Complete Flag.
Set to 1 by hardware to indicate a LHS reset command has completed successfully.
Cleared to 0, after user code reads the LHSSTA MMR.
Break Field Error.
Set to 1 by hardware and generates an LHS interrupt (IRQEN[7]) when the 12-bit break timer (LHSVAL1) register
overflows to indicate the LIN bus has stayed low too long, thus indicating a possible LIN bus error.
Cleared to 0, after user code reads the LHSSTA MMR.
LHS Compare Interrupt.
Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) = the value in the LHSCMP register.
Cleared to 0, after user code reads the LHSSTA MMR.
Stop Condition Interrupt.
Set to 1 by hardware when a stop condition is detected.
Cleared to 0, after user code reads LHSSTA MMR.
Start Condition Interrupt.
Set to 1 by hardware when a start condition is detected.
Cleared to 0, after user code reads LHSSTA MMR.
Break Timer Compare Interrupt.
Set to 1 by hardware when a valid LIN break condition is detected. A LIN break condition is generated when the LIN
break timer value reaches the break timer compare value (see LHSVAL1 in the LIN Hardware Break Timer1 Register
section for more information).
Cleared to 0 after user code reads the LHSSTA MMR.
Rev. B | Page 122 of 140