ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 60

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
ADC Comparator and Accumulator
Every I-ADC result can also be compared to a preset threshold
level (ADC0TH) as configured via ADCCFG[4:3]. An MCU
interrupt is generated if the absolute (sign independent) value
of the ADC result is greater than the preprogrammed com-
parator threshold level. An extended function of this comparator
function allows user code to configure a threshold counter
(ADC0THV) to monitor the number of I-ADC results that have
occurred above or below the preset threshold level. Again, an
ADC interrupt is generated when the threshold counter reaches
a preset value (ADC0TCL).
Finally, a 32-bit accumulator (ADC0ACC) function can be
configured (ADCCFG[6:5]) allowing the I-ADC to add (or
subtract) multiple I-ADC sample results. User code can read the
accumulated value directly (ADC0ACC) without any further
software processing.
ADC Sinc3 Digital Filter Response
The overall frequency response on all ADuC7033 ADCs is
dominated by the low-pass filter response of the on-chip Sinc3
digital filters. The Sinc3 filters are used to decimate the ADC
Σ-Δ modulator output data bit stream to generate a valid 16-bit
data result. The digital filter response is identical for all ADCs
and is configured via the 16-bit ADC filter (ADCFLT) register. This
register determines the overall throughput rate of the ADCs. The
noise resolution of the ADCs is determined by the programmed
ADC throughput rate. In the case of the current channel ADC,
the noise resolution is determined by the throughput rate and
selected gain.
The overall frequency response and the ADC throughput is
dominated by the configuration of the Sinc3 filter decimation
factor (SF) bits (ADCFLT[6:0]) and the averaging factor (AF)
bits (ADCFLT[13:8]). Due to limitations on the digital filter
internal data path, there are some limitations on the allowable
combinations of SF and AF that can be used to generate a
required ADC output rate. This restriction limits the minimum
ADC update in normal power mode to 4 Hz or 1 Hz in low
power mode. The calculation of the ADC throughput rate is
detailed in the ADCFLT bit designations table (see Table 39) and
the restrictions on allowable combinations of AF and SF values
are outlined in Table 41.
By default, the ADCFLT = 0x07 configures the ADCs for a
throughput of 1.0 kHz with all other filtering options (chop,
running average, averaging factor, and Sinc3 modify) disabled.
A typical filter response based on this default configuration is
shown in Figure 21.
Rev. B | Page 60 of 140
An additional Sinc3 modify bit (ADCFLT[7]) is also available
in the ADCFLT register. This bit is set by user code to modify
the standard Sinc3 frequency response increasing the filter stop-
band rejection by approximately 5 dB. This is achieved by inserting
a second notch (NOTCH2) at
where f
There is a slight increase in ADC noise if this bit is active.
Figure 22 shows the modified 1 kHz filter response when the
Sinc3 modify bit is active. The new notch is clearly visible at
1.33 kHz, as is the improvement in stop-band rejection when
compared to the standard 1 kHz response.
In ADC normal power mode, the maximum ADC throughput
rate is 8 kHz. This is configured by setting the SF and AF bits in
the ADCFLT MMR to 0, with all other filtering options disabled.
This results in 0x0000 written to ADCFLT. A typical 8 kHz filter
response based on these settings is shown in Figure 23.
f
–100
–100
Figure 22. Modified Sinc3 Digital Filter Response at f
NOTCH2
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
NOTCH
0
0
Figure 21. Typical Digital Filter Response at f
0
0
= 1.333 × f
is the location of the first notch in the response.
500
0.5
1000 1500 2000 2500 3000 3500 4000 4500 5000
1.0
NOTCH
1.5
(ADCFLT = 0x0007)
(ADCFLT = 0x0087)
FREQUENCY (kHz)
FREQUENCY (kHz)
2.0
2.5
3.0
3.5
ADC
4.0
= 1.0 kHz
ADC
= 1.0 kHz
4.5
5.0