ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 9

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Not guaranteed by production test, but by design and/or characterization data at production release.
Valid for current ADC gain setting of PGA = 4 to 64.
These numbers include temperature drift.
Tested at gain range = 4; self-offset calibration removes this error at the operating temperature.
Measured with an internal short after an initial offset calibration.
Measured with an internal short.
These numbers include internal reference temperature drift.
Factory calibrated at gain = 1.
System calibration at a specific gain range removes the error at this gain range at that temperature.
1 kHz update rate chop enable is achieved with ADCFLT = 0x8101; yet with chop off, ADCFLT = 0x0007, unless otherwise stated.
Typical noise in low power modes is measured with chop enabled.
Voltage channel specifications include resistive attenuator input stage.
Includes an initial system calibration.
System calibration removes this error.
RMS noise is referred to voltage attenuator input, for example, at f
ADC self-offset calibration removes this error at the operating temperature.
Valid after an initial self calibration.
In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV.
It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach
can also be used to reduce the ADC input range (LSB size).
Limited by minimum/maximum absolute input voltage range.
Valid for a differential input less than 10 mV.
Measured using box method.
The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000-hour period.
References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2.
Die temperature.
Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
Retention lifetime equivalent at junction temperature (T
Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code.
These numbers are not production tested, but are supported by LIN compliance testing.
BSD electrical specifications, except high and low voltage levels, are per LIN 2.0 with pull-up resistor disabled and C
Specified after R
The MCU core is not shut down but interrupted, and high voltage I/O pins are disabled in response to a thermal shutdown event.
Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature.
Internal regulated supply available at REG_DVDD (I
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
input referred noise figures.
LIMIT
of 39 Ω.
SOURCE
J
= 5 mA), and REG_AVDD (I
) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
ADC
= 1 kHz, typical rms noise at the ADC input is 7.5 μV, scaled by the attenuator (24) yields these
Rev. B | Page 9 of 140
SOURCE
= 1 mA).
Load
= 10 nF maximum.
ADuC7033