ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 115

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Control Register
Name:
Address:
Default Value:
Access:
Function:
Table 89. SPICON MMR Bit Designations
Bit
15 to 13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPICON
0xFFFF0A10
0x0000
Read/write
The 16-bit MMR configures the serial peripheral interface.
Description
Reserved.
Continuous Transfer Enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, a new transfer is initiated after a stall period.
Loopback Enable.
Set by user to connect MISO to MOSI and test software.
Cleared by user to be in normal mode.
Slave Output Enable.
Set by user to enable the slave output.
Cleared by user to disable slave output.
Slave Select Input Enable.
Set by user in master mode to enable the output.
SPIRX Overflow Overwrite Enable.
Set by the user, the valid data in the SPIRX register is overwritten by the new serial byte received.
Cleared by the user, the new serial byte received is discarded.
SPITX Underflow Mode.
Set by the user to transmit the previous data.
Cleared by the user to transmit 0.
Transfer and Interrupt Mode (Master Mode).
Set by the user to initiate a transfer with a write to the SPITX register. Interrupt occurs when SPITX is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt occurs when SPIRX is full.
LSB First Transfer Enable Bit.
Set by the user; the LSB is transmitted first.
Cleared by the user; the MSB is transmitted first.
Reserved. Should be written as 0.
Serial Clock Polarity Mode Bit.
Set by user, the serial clock idles high.
Cleared by user the serial clock idles low.
Serial Clock Phase Mode Bit.
Set by the user. The serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user. The serial clock pulses at the end of each serial bit transfer.
Master Mode Enable Bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
SPI Enable Bit.
Set by the user to enable the SPI.
Cleared to disable the SPI.
Rev. B | Page 115 of 140
ADuC7033