ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 93
ADUC7033BCPZ-8L-RL
Manufacturer Part Number
ADUC7033BCPZ-8L-RL
Description
IC MCU FLASH 96K ANLG I/O 48LFCS
Manufacturer
Analog Devices Inc
Type
Battery Managementr
Specifications of ADUC7033BCPZ-8L-RL
Input Type
Logic
Output Type
Logic
Interface
UART, SPI
Current - Supply
20mA
Mounting Type
Surface Mount
Package / Case
*
For Use With
EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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GPIO Port0 Data Register
Name:
Address:
Default Value:
Access:
Function:
Table 62. GP0DAT MMR Bit Designations
Bit
31 to 29
28
27
26
25
24
23 to 21
20
19
18
17
16
15 to 5
4
3
2
1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port0.4 Direction Select Bit.
Cleared to 0 by user code to configure the GPIO pin assigned to Port0.4 as an input.
Set to 1 by user code to configure the GPIO pin assigned to Port0.4 as an output.
Port0.3 Direction Select Bit.
Cleared to 0 by user code to configure the GPIO pin assigned to Port0.3 as an input.
Set to 1 by user code to configure the GPIO pin assigned to Port0.3 as an output.
Port0.2 Direction Select Bit.
Cleared to 0 by user code to configure the GPIO pin assigned to Port0.2 as an input.
Set to 1 by user code to configure the GPIO pin assigned to Port0.2 as an output.
Port0.1 Direction Select Bit.
Cleared to 0 by user code to configure the GPIO pin assigned to Port0.1 as an input.
Set to 1 by user code to configure the GPIO pin assigned to Port0.1 as an output.
Port0.0 Direction Select Bit.
Cleared to 0 by user code to configure the GPIO pin assigned to Port0.0 as an input.
Set to 1 by user code to configure the GPIO pin assigned to Port0.0 as an output.
Reserved. These bits are reserved and should be written as 0 by user code.
Port0.4 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.4.
Port0.3 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.3.
Port0.2 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.2.
Port0.1 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.1.
Port0.0 Data Output. The value written to this bit appears directly on the GPIO pin assigned to Port0.0.
Reserved. These bits are reserved and should be written as 0 by user code.
Port0.4 Data Input. This bit is a read-only bit that reflects the current status of the GPIO pin assigned to Port0.4. User code should
write 0 to this bit.
Port0.3 Data Input. This bit is a read-only bit that reflects the current status of the GPIO pin assigned to Port0.3. User code should
write 0 to this bit.
Port0.2 Data Input. This bit is a read-only bit that reflects the current status of the GPIO pin assigned to Port0.2. User code should
write 0 to this bit.
Port0.1 Data Input. This bit is a read-only bit that reflects the current status of the GPIO pin assigned to Port0.1. User code should
write 0 to this bit.
Port0.0 Data Input. This bit is a read-only bit that reflects the current status of the GPIO pin assigned to Port0.0. User code should
write 0 to this bit.
GP0DAT
0xFFFF0D20
0x000000XX
Read/write
This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 58). This register also sets the
output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Rev. B | Page 93 of 140
ADuC7033
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