ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 119

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 91. STICON MMR Bit Designations
Bit
16 to 9
8 to 5
4 to 2
1
0
Serial Test Interface Output Structure
The serial test interface is a high voltage output that
incorporates a low-side driver, short-circuit protection, and
diagnostic pin readback capability. The output driver circuit
configuration is shown in Figure 4 .
Using the Serial Test Interface
Data only begins transmission when configuration of the STI
port has been completed in the following sequence:
1.
2.
3.
Timer4 is configured with the correct load value to generate an
overflow at the required baud rate. If the STI port is being used
to transmit ADC conversion results, the baud rate must be
sufficient to output each ADC result (16-bits) prior to the next
ADC conversion result being available.
Configure Timer4 for baud rate generation.
Correctly enable STICON using STIKEY0 and STIKEY1
for secure access.
Required bytes to be transmitted are written into
STIDAT0, STIDAT1, and STIDAT2.
GP2CON[24]
READBACK
TRANSMIT
HVMON[5]
PIN
STI
Description
Reserved. These bits are reserved for future use and should be written as 0 by user code.
State Bits, Read Only. If the interface is in the middle of a transmission, these bits are not 0.
Number of Bytes to Transmit. These bits select the number of bytes to be transmitted. User code must subsequently
write the bytes to be transmitted into the STIDAT0, STIDAT1, and STIDAT2 MMRs.
000 = 1-byte transmission.
001 = 2-byte transmission.
010 = 3-byte transmission.
011 = 4-byte transmission.
100 = 5-byte transmission.
101 = 6-byte transmission.
Reset Serial Test Interface.
Set to 1 to reset the serial test interface; a subsequent read of STICON returns all 0s.
This bit is 0 by default to operate in normal mode.
Serial Test Interface Enable.
Set to 1 by user code to enable the serial test interface.
Set to 0 by user code to disable the serial test interface.
Figure 44. STI Output Structure
PROTECTION CONTROL
SHORT-CIRCUIT
HVCFG1[2]
REF1
STI
Rev. B | Page 119 of 140
For example, if the ADC is sampling at 1 kHz, then the baud
rate has to be sufficient to output 36 bits as follows:
Therefore, the serial test interface must transmit data at greater
than 36 kbps. The closest standard baud rate is 38.4 kbps; as
such, the reload value written to the Timer4 load MMR (T4LD)
is 0x0106 (267 decimal). This value is calculated as follows, and
is based on a prescaler of 1, using a core clock of 10.24 MHz:
When the Timer4 load value is written and the timer itself
is configured and enabled using the T4CON MMR, the STI
port must be configured. This is accomplished by writing to the
STICON MMR in a specific sequence using the STIKEY0 and
STIKEY1 MMRs as previously described throughout the Serial
Test Interface section.
Finally, the STI port does not begin transmission until the
required number of transmit bytes are written into the
STIDATx MMRs. As soon as STI starts transmitting, the
value in the STICON MMR changes from the value initially
written to this register. User code can ensure that all data is
transmitted by continuously polling the STICON MMR until
it reverts back to the value originally written to it. To disable
the serial interface, user code must write a 0 to STICON[0].
(3 × 8 bits (16-bit ADC result and a checksum byte, for
example)) + (3 × 1 start bit) + (3 × 1 parity bit) +
(3 × 2 stop bits) = 36 bits
T4LD
=
Core
Desired
Clock
Baud
Frequency
Rate
=
10
38
.
24
4 .
kbps
MHz
ADuC7033
=
267