ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 27

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User software must ensure that the Flash/EE memory controller
has completed any erase or write cycle before the PLL is
powered down. If the PLL is powered down before an erase or
FEE0CON and FEE1CON Registers
Name:
Address:
Default Value:
Access:
Function:
Table 13. Command Codes in FEE0CON and FEE1CON
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
1
2
x is 0 or 1 to designate Flash/EE memory Block0 or Block1.
The FEExCON always reads 0x07 immediately after execution of any of these commands.
2
2
2
2
2
2
2
Reserved
Reserved
Reserved
Signature
Reserved
Reserved
Command
Reserved
Single Read
Single Write
Erase-Write
Single Verify
Single Erase
Mass Erase
Protect
Ping
FEE0CON and FEE1CON
0xFFFF0E08 and 0xFFFF0E88
0x07
Read/write access
These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for
Block0 (32 kB) and Block1 (64 kB).
Description
Reserved, this command should not be written by user code.
Load FEExDAT with the 16-bit data indexed by FEExADR.
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation
takes 20 ms.
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison
is returned in FEExSTA Bit 1.
Erase the page indexed by FEExADR.
Erase Block0 (30 kB) or Block1 (64 kB) of user space. The 2 kB kernel is protected. This operation takes 1.2 sec. To
prevent accidental execution, a command sequence is required to execute this instruction, this is described in
the following command codes.
Default command.
Reserved, this command should not be written by user code.
Reserved, this command should not be written by user code.
Reserved, this command should not be written by user code.
FEE0CON: This command results in a 24-bit LFSR-based signature being generated and loaded into FEE0SIG.
If FEE0ADR is less than 0x97800, this command results in a 24-bit LFSR-based signature of the user code space
from the page specified in FEE0ADR upwards, including the kernel, security bits, and the Flash/EE memory key.
If FEE0ADR is greater than 0x97800, the kernel and manufacturing data is signed. This operation takes 120 μs.
FEE1CON: This command results in a 24-bit LFSR based signature been generated, beginning at FEE1ADR and
ending at the end of the 64 kB block, and loaded into FEE1SIG. The last page of this block is not included in the
sign generation.
This command can be run only one time. The value of FEExPRO is saved and can be removed only with a mass
erase (0x06) or with the key.
Reserved, this command should not be written by user code.
Reserved, this command should not be written by user code.
No operation, interrupt generated.
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write cycle is completed, the Flash/EE page or byte may be
corrupted.
The following sections provide detailed descriptions of the bit
designations for each of the Flash/EE memory control MMRs.
ADuC7033