ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 41

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 27. STI Base Address = 0xFFFF0880
Address
0x0880
0x0884
0x0888
0x088C
0x0890
0x0894
Table 28. SPI Base Address = 0xFFFF0A00
Address
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
Table 29. GPIO Base Address = 0xFFFF0D00
Address
0x0D00
0x0D04
0x0D08
0x0D20
0x0D24
0x0D28
0x0D30
0x0D34
0x0D38
0x0D40
0x0D44
0x0D48
1
Depends on the level on the external GPIO pins.
Name
STIKEY0
STICON
STIKEY1
STIDAT0
STIDAT1
STIDAT2
Name
GP0CON
GP1CON
GP2CON
GP0DAT
GP0SET
GP0CLR
GP1DAT
GP1SET
GP1CLR
GP2DAT
GP2SET
GP2CLR
Name
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
1
1
1
Byte
4
2
4
2
2
2
Byte
Byte
1
1
1
1
2
4
4
4
4
4
4
4
4
4
4
4
4
Access
Type
W
RW
W
RW
RW
RW
Access
Type
R
R
W
RW
RW
Access
Type
RW
RW
RW
RW
W
W
RW
W
W
RW
W
W
Default Value
N/A
0x0000
N/A
0x0000
0x0000
0x0000
Default Value
0x00
0x00
0x1B
0x0000
Default Value
0x11100000
0x10000000
0x01000000
0x000000XX
0x000000XX
0x000000XX
Rev. B | Page 41 of 140
Description
STICON Prewrite Key. See the Serial Test Interface Key0 Register section.
Serial Test Interface Control MMR. See the Serial Test Interface Control
Register section.
STICON Postwrite Key. See the Serial Test Interface Key1 Register section
and Table 91.
STI Data MMR 0. See the Serial Test Interface Data0 Register section.
STI Data MMR 1. See the Serial Test Interface Data1 Register section.
STI Data MMR 2. See the Serial Test Interface Data2 Register section.
Description
SPI Status MMR. See the SPI Status Register section and Table 90.
SPI Receive MMR. See the SPI Receive Register section.
SPI Transmit MMR. See the SPI Transmit Register section.
SPI Baud Rate Select MMR. See the SPI Divider Register section.
SPI Control MMR. See the SPI Control Register section and Table 89.
Description
GPIO Port0 Control MMR. See the GPIO Port0 Control Register section
and Table 59.
GPIO Port1 Control MMR. See the GPIO Port1 Control Register section
and Table 60.
GPIO Port2 Control MMR. See the GPIO Port2 Control Register section
and Table 61.
GPIO Port0 Data Control MMR. See the GPIO Port0 Data Register section
and Table 62.
GPIO Port0 Data Set MMR. See the GPIO Port0 Set Register section and
Table 65.
GPIO Port0 Data Clear MMR. See the GPIO Port0 Clear Register section
and Table 68.
GPIO Port1 Data Control MMR. See the GPIO Port1 Data Register section
and Table 63.
GPIO Port1 Data Set MMR. See the GPIO Port1 Set Register section and
Table 66.
GPIO Port1 Data Clear MMR. See the GPIO Port1 Clear Register section
and Table 69.
GPIO Port2 Data Control MMR. See the GPIO Port2 Data Register section
and Table 64.
GPIO Port2 Data Set MMR. See the GPIO Port2 Set Register section and
Table 67.
GPIO Port2 Data Clear MMR. See the GPIO Port2 Clear Register section
and Table 70.
ADuC7033