ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 125

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIN Hardware Synchronization Control Register 1
Name:
Address:
Default Value:
Access:
Function:
Table 95. LHSCON1 MMR Bit Designations
Bit
31 to 8
7 to 4
3 to 0
LIN Hardware Synchronization Timer0 Register
Name:
Address:
Default Value:
Access:
Function:
LIN Hardware Break Timer1 Register
Name:
Address:
Default Value:
Access:
Function:
LHSCON1
0xFFFF078C
0x32
Read/write
The LHS control register is a 32-bit register that, in conjunction with the LHSCON0 register, is used to configure the
LIN mode of operation.
LHSVAL0
0xFFFF0788
0x0000
Read/write
The 16-bit, read-only register holds the value of the internal LIN synchronization timer. The LIN synchronization
timer is clocked from an internal 5 MHz clock and is independent of core clock and baud rate frequency. In LIN
mode, the value read by user code from the LHSVAL0 register can be used calculate the master LIN baud rate. This
calculation is then used to configure the internal UART baud rate to ensure correct LIN communication via the UART
from the ADuC7033 slave to the LIN master node.
LHSVAL1
0xFFFF0790
0x0000 (default), 0x0000 (read), or 0x0047 (write)
Read/write
When user code reads this location, the 12-bit value returned is the value of the internal LIN break timer, which is
clocked directly from the on-chip low power (131 kHz) oscillator and times the LIN break pulse. A negative edge on
the LIN bus or user code reading the LHSVAL1 results in the timer and the register contents being reset to 0.When
user code writes to this location, the 12-bit value is written not to the LIN break timer, but to a LIN break compare
register. In LIN mode of operation, the value in the compare register is continuously compared to the break timer
value. A LIN break interrupt (IRQEN[7] and LHSSTA[0]) is generated when the timer value reaches the compare
value. After the break condition interrupt, the LIN break timer continues to count until the rising edge of the break
signal. If a rising edge is not detected and the 12-bit timer overflows (4096 × 1/131 kHz = 31 ms), a break field error
interrupt (IRQEN[7] and LHSSTA[4]) is generated. By default, the value in the compare register is 0x47 corresponding
to 11 bit periods, that is, the minimum pulse width for a LIN break pulse at 20 kbps. For different baud rates, this value
can be changed by writing to LHSVAL1. Note that if a valid break interrupt is not received, then subsequent sync pulse
timing through the LHSVAL0 register does not occur.
Description
Reserved. These bits are reserved for future use and should be written as 0 by user software.
LIN Stop Edge Count. These bits are set by user code to the number of falling or rising edges on which to stop the
internal LIN synchronization counter. The stop value of this counter can be read by user code using LHSVAL0. The type
of edge, either rising or falling, is configured by LHSCON0[7]. The default value of these bits is 0x3, which configures the
hardware to stop counting on the third falling edge. Note that the first falling edge is taken as the falling edge at the
start of the LIN break pulse.
LIN Start Edge Count. These four bits are set by user code to the number of falling edges after which the internal LIN
synchronization timer starts counting. The stop value of this counter can be read by user code using LHSVAL0. The
default value of these bits is 0x2, which configures the hardware to start counting on the second falling edge. Note
that the first falling edge is taken as the falling edge at the start of the LIN break pulse.
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ADuC7033