ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 126

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
LIN HARDWARE INTERFACE
LIN Frame Protocol
The LIN frame protocol is broken into four main categories:
break symbol, sync byte, protected identifier, and data bytes.
The format of the frame header, break, synchronization byte,
and protected identifier are shown in Figure 4 . Essentially, the
embedded UART, LIN hardware synchronization logic, and the
high voltage transceiver interface all combine on-chip to support
and manage LIN-based transmissions and receptions.
LIN Frame Break Symbol
As shown in Figure 4 , the LIN break symbol is used to signal
the start of a new frame. It lasts at least 13 bit periods and a
slave must be able to detect a break symbol, even if it expects
data or is in the process of receiving data. The ADuC7033
accomplishes this by using the LHSVAL1 break condition and
break error detect functionality as previously described. The
break period does not have to be accurately measured, but if a
bus fault condition (bus held low) occurs, it must be flagged.
LIN Frame Synchronization Byte
The baud rate of the communication using LIN is calculated
from the sync byte, as shown in Figure 4 . The time between
the first falling edge of the sync field and the fifth falling edge
of the sync field is measured. This result is divided by 8 to give
the baud rate of the data that is going to be transmitted. The
ADuC7033 implements the timing of this sync byte in hard-
ware. For more information on this feature, refer to the LIN
Hardware Synchronization Status Register section.
LIN Frame Protected Identifier
After receiving the LIN sync field, the required baud rate for the
UART is calculated. The UART is then configured, allowing the
ADuC7033 to receive the protected identifier, as shown in
Figure 4 . The protected identifier consists of two subfields: the
identifier and the identifier parity. The 6-bit identifier contains
the identifier of the target for the frame. The identifier signifies
the number of data bytes to be either received or transmitted.
The number of bytes is user-configurable at the system level
design. The parity is calculated on the identifier, and is
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dependent on the revision of LIN for which the system is
designed.
LIN Frame Data Byte
The data byte frame carries between one and eight bytes of data.
The number of bytes contained in the frame is dependent on
the LIN master. The data byte frame splits into data bytes, as
shown in Figure
LIN Frame Data Transmission and Reception
When the break symbol and synchronization byte have been
correctly received, data is transmitted and received via the
COMTX and COMRX MMRs, after configuration of the UART
to the required baud rate. To configure the UART for use with
LIN requires the use of the following UART MMRs:
COMDIV0: divisor latch (low byte).
COMDIV1: divisor latch (high byte).
COMDIV2: 16-bit fractional baud divide register. The required
values for COMDIV0, COMDIV1, and COMDIV2 are derived
from the LHSVAL0 to generate the required baud rate.
COMCON0 is a line control register. As soon as the UART is
correctly configured, the LIN protocol for receiving and
transmitting data is identical to the UART specification.
To manage data on the LIN bus requires use of the following
UART MMRs:
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•
•
•
Transmitting data on the LIN bus requires that the relevant data
be placed into COMTX. Reading data received on the LIN bus
requires the monitoring of COMRX. To ensure that data is
received or transmitted correctly, COMSTA0 is monitored.
For more information refer to the UART Serial Interface and
UART Register Definition sections of this data sheet.
Under software control, it is possible to multiplex the UART
data lines (TxD and RxD) to the external GPIO pins (GPIO_7
and GPIO_8). For more information, refer to the description of
the GPIO Port1 Control Register (GP1CON) section.
COMTX: 8-bit transmit register.
COMRX: 8-bit receive register.
COMCON0: line control register.
COMSTA0: line status register.
.