ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 61

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A modified version of the 8 kHz filter response can be
configured by setting the running average bit (ADCFLT[14]).
This has the effect of introducing an additional running-average-
by-two filter on all ADC output samples. This further reduces
the ADC output noise and by maintaining an 8 kHz ADC
throughput rate, the ADC settling time is increased by one
full conversion period. The modified frequency response for
this configuration is shown in Figure 24.
At very low throughput rates, the chop bit in the ADCFLT
register can be enabled to minimize offset errors and, more
importantly, temperature drift in the ADC offset error. With
chop enabled, there are two primary variables (Sinc3 decimation
factor and averaging factor) available to allow the user to select
an optimum filter response, trading off filter bandwidth against
ADC noise.
For example, with the Chop Enable Bit ADCFLT[15] set to 1,
increasing the SF value (ADCFLT[6:0]) to 0x1F (31 decimal)
and selecting an AF value (ADCFLT[13:8]) of 0x16
(22 decimal) results in an ADC throughput of 10 Hz. The
frequency response in this case is shown in Figure 25.
Figure 23. Typical Digital Filter Response at f
Figure 24. Typical Digital Filter Response at f
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
2
2
4
4
6
6
8
FREQUENCY (kHz)
8
10
FREQUENCY (kHz)
10
12
12
14
14
ADC
ADC
16
= 8 kHz (ADCFLT = 0x0000)
= 8 kHz (ADCFLT = 0x4000)
16
18
18
20
20
22
22
24
24
Rev. B | Page 61 of 140
Changing SF to 0x1D and setting AF to 0x3F with the chop bit
enabled configures the ADC into its minimum throughput rate
in normal mode of 4 Hz. The digital filter frequency response
with this configuration is shown in Figure 26.
In ADC low power mode, the ADC, Σ-Δ modulator clock is no
longer driven at 512 kHz, but is driven directly from the on-
chip low power (131 kHz) oscillator. Subsequently, for the same
ADCFLT configurations in normal mode, all filter values
should be scaled by a factor of approximately four. This means
that it is possible to configure the ADC for 1 Hz throughput in
low power mode. The filter frequency response for this
configuration is shown in Figure 27.
Figure 25. Typical Digital Filter Response at f
Figure 26. Typical Digital Filter Response at f
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
20
40
60
20
FREQUENCY (Hz)
FREQUENCY (Hz)
80
100
120
ADC
ADC
= 10 Hz (ADCFLT = 0x961F)
= 4 Hz (ADCFLT = 0xBF1D)
40
140
160
ADuC7033
180
200
6
0