ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 22

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
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Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define interrupts
as the FIQ type.
The priority of these exceptions and vector addresses are listed
in Table 9.
Table 9. Exception Priorities and Vector Addresses
Priority
1
2
3
4
5
6
6
1
The list of exceptions in Table 9 are located from 0x00 to 0x1C,
with a reserved location at 0x14. This location must be written
with either 0x27011970 or the checksum of Page Zero, excluding
Location 0x14. If this is not done, user code does not execute
and LIN download mode is entered.
ARM Registers
The ARM7TDMI has 16 standard registers. R0 to R12 are for
data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (if the branch
and link command was used) or the command during which an
exception occurred.
The stack pointer contains the current location of the stack.
Generally, on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends using the area as required. A
separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. On the ADuC7033, the stack begins at 0x00040FFC
and descends. When programming using high level languages,
such as C, it is necessary to ensure that the stack does not overflow.
This is dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
priority and are mutually exclusive.
A software interrupt and an undefined instruction exception have the same
Normal interrupt (IRQ). This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt (FIQ). This is provided to service data
transfer or a communication channel with low latency. FIQ
has priority over IRQ.
Memory abort (prefetch and data).
Attempted execution of an undefined instruction.
Software interrupt (SWI) instruction that can be used to
make a call to an operating system.
Exception
Hardware Reset
Memory Abort (Data)
FIQ
IRQ
Memory Abort (Prefetch)
Software Interrupt
Undefined Instruction
1
1
Address
0x00
0x10
0x1C
0x18
0x0C
0x08
0x04
Rev. B | Page 22 of 140
in Figure 11. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly
from ARM Ltd.
Interrupt Latency
The worst-case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest instruc-
tion is an LDM) that loads all the registers including the PC, plus
the time for the data abort entry, plus the time for FIQ entry. At
the end of this time, the ARM7TDMI is executing the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum total
time is 50 processor cycles, or just over 2.44 μs in a system using
a continuous 20.48 MHz processor clock. The maximum IRQ
latency calculation is similar, but must allow for the fact that FIQ
has higher priority and can delay entry into the IRQ handling
routine for an arbitrary length of time. This time can be reduced
to 42 cycles if the LDM command is not used; some compilers
have an option to compile without using this command. Another
option is to run the part in Thumb mode where this is reduced
to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if
required, for example, when executing interrupt service
routines.
USER MODE
R15 (PC)
CPSR
R10
R11
R12
R13
R14
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
SPSR_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
Figure 11. Register Organization
R8_FIQ
R9_FIQ
MODE
FIQ
SPSR_SVC
R13_SVC
R14_SVC
MODE
SVC
SPSR_ABT
R13_ABT
R14_ABT
ABORT
MODE
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_IRQ
R13_IRQ
R14_IRQ
MODE
IRQ
UNDEFINED
SPSR_UND
R13_UND
R14_UND
MODE