ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 88

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7033 features nine general-purpose bidirectional
input/output (GPIO) pins. In general, many of the GPIO pins
have multiple functions that can be configured by user code. By
default, the GPIO pins are configured in GPIO mode. All GPIO
pins have an internal pull-up resistor with a sink capability of
0.8 mA and a source capability of 0.1 mA.
The nine GPIOs are grouped into three ports: Port0, Port1, and
Port2. Port0 is five bits wide. Port1 and Port2 are both two bits
wide. The GPIO assignment within each port is detailed in
Table 58. A typical GPIO structure is shown Figure 39.
External interrupts are present on GPIO_0, GPIO_5, GPIO_7,
and GPIO_8. These interrupts are level triggered and are active
high. These interrupts are not latched; therefore, the interrupt
source must be present until either IRQSTA or FIQSTA are
interrogated. The interrupt source must be active for at least
one CD divided core clock to guarantee recognition.
Rev. B | Page 88 of 140
All port pins are configured and controlled by four sets (one set
for each port) of four port-specific MMRs as follows:
•
•
•
•
where x corresponds to the port number (0, 1, or 2).
During normal operation, user code can control the function
and state of the external GPIO pins by these general-purpose
registers. All GPIO pins retain their external level (high or low)
during power-down (POWCON) mode.
GPxCON: Portx control register
GPxDAT: Portx configuration and data register
GPxSET: Data Set Portx
GPxCLR: Data Clear Portx
OUTPUT DRIVE ENABLE
1
ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8.
GPxDAT[31:24]
GPxDAT[23:16]
OUTPUT DATA
GPxDAT[7:0]
INPUT DATA
GPIO IRQ
Figure 39. ADuC7033 GPIO
1
REG_DVDD
GPIO