ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 37

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

COMPLETE MMR LISTING
In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write.
Table 19. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0100
0x0104
0x0108
0x010C
1
Table 20. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
0x0234
0x0238
0x023C
0x0240
1
Table 21. Timer Address Base = 0xFFFF0300
Address
0x0300
0x0304
0x0308
0x030C
0x0310
0x0314
0x0320
0x0324
0x0328
0x032C
0x0330
Depends on the level on the external interrupt pins (GPIO_0, GPIO_5, GPIO_7, and GPIO_8).
Updated by kernel.
Name
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
FIQSTA
FIQSIG
FIQEN
FIQCLR
Name
SYSMAP0
RSTSTA
RSTCLR
SYSSER0
SYSSER1
SYSCHK
Name
T0LD
T0VAL0
T0VAL1
T0CON
T0CLRI
T0CAP
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
1
1
1
1
1
Byte
4
4
4
4
4
4
4
4
4
Byte
1
1
1
4
4
4
Byte
2
2
4
4
1
2
4
4
4
1
4
Access
Type
R
R
RW
W
W
R
R
RW
W
Access
Type
RW
RW
W
RW
RW
RW
Access
Type
RW
R
R
RW
W
RW
RW
R
RW
W
R
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
Default Value
0x0000
0x0000
0x00000000
0x00000000
N/A
0x0000
0x00000000
0xFFFFFFFF
0x01000000
N/A
0x00000000
Rev. B | Page 37 of 140
REMAP Control Register. See the Remap Operation section and Table 10.
RSTSTA Clear MMR. See the Reset section and Table 11 and Table 12.
System Serial Number 0. See the Part Identification section and Table 99 for
details.
System Serial Number 1. See the Part Identification section and Table 100 for
details.
Kernel Checksum. See the System Kernel Checksum section.
Description
Active IRQ Source. See the Interrupt System section and Table 50.
Current State of All IRQ Sources (Enabled and Disabled). See the Interrupt
System section and Table 50.
Enabled IRQ Sources. See the Interrupt System section and Table 50.
MMR to Disable IRQ Sources. See the Interrupt System section and Table 50.
Software Interrupt Configuration MMR. See the Programmed Interrupts
section and Table 51.
Active IRQ Source. See the Interrupt System section and Table 50.
Current State of All IRQ Sources (Enabled and Disabled). See the Interrupt
System section and Table 50.
Enabled IRQ Sources. See the Interrupt System section and Table 50.
MMR to Disable IRQ Sources. See the Interrupt System section and Table 50.
Description
Reset Status MMR. See the Reset section and Table 11 and Table 12.
Description
Timer0 Load Register. See the Timer0—Lifetime Timer and Timer0 Load
Registers sections.
Timer0 Value Register 0. See the Timer0—Lifetime Timer and Timer0 Value
Registers (T0VAL0/T0VAL1) sections.
Timer0 Value Register 1. See the Timer0—Lifetime Timer and Timer0 Value
Registers (T0VAL0/T0VAL1) sections.
Timer0 Control MMR. See the Timer0—Lifetime Timer and Timer0 Control
Register sections.
Timer0 Interrupt Clear Register. See the Timer0—Lifetime Timer and Timer0
Clear Register sections.
Timer0 Capture Register. See the Timer0—Lifetime Timer and Timer0 Capture
Register sections.
Timer1 Load Register. See the Timer1 and Timer1 Load Registers sections.
Timer1 Value Register. See the Timer1 and Timer1 Value Register sections.
Timer1 Control MMR. See the Timer1 and Timer1 Control Register sections.
Timer1 Interrupt Clear Register. See the Timer1 and Timer1 Clear Register
sections.
Timer1 Capture Register. See the Timer1 and Timer1 Capture Register sections.
ADuC7033