ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 10

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ADUC7033BCPZ-8L-RL

Manufacturer Part Number
ADUC7033BCPZ-8L-RL
Description
IC MCU FLASH 96K ANLG I/O 48LFCS
Manufacturer
Analog Devices Inc
Type
Battery Managementr
Datasheets

Specifications of ADUC7033BCPZ-8L-RL

Input Type
Logic
Output Type
Logic
Interface
UART, SPI
Current - Supply
20mA
Mounting Type
Surface Mount
Package / Case
*
For Use With
EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC7033
TIMING SPECIFICATIONS
SPI Timing Specifications
Table 2. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider (CD) bits in POWCON MMR. t
= 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SCLK
SCLK
MOSI
MISO
1
1
t
DAV
t
SH
Figure 2. SPI Master Mode Timing (PHASE Mode = 1)
2
t
DSU
HCLK
2
MSB IN
= t
MSB
t
DHD
UCLK
t
Rev. B | Page 10 of 140
SL
/2
CD
t
.
DF
Min
0
3 × t
UCLK
t
DR
BITS [6:1]
BITS [6:1]
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
3.5
3.5
3.5
3.5
t
SR
HCLK
HCLK
t
LSB IN
SF
Max
(2 × t
LSB
UCLK
) + (2 × t
HCLK
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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