ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 65

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER SUPPLY SUPPORT CIRCUITS
The ADuC7033 incorporates two on-chip, low dropout (LDO)
regulators that are driven directly from the battery voltage to
generate a 2.6 V internal supply. This 2.6 V supply is then used
as the supply voltage for the ARM7 MCU and peripherals
including the precision analog circuits on-chip.
The digital LDO functions with two output capacitors, 2.2 μF
and 0.1 μF in parallel, on REG_DVDD, whereas the analog
LDO functions with an output capacitor (0.47 μF) on
REG_AVDD.
The ESR of the output capacitor affects stability of the LDO
control loop. An ESR of 5 Ω or less for frequencies above 32 kHz
is recommended to ensure the stability of the regulators.
Power-on-reset (POR), power supply monitor (PSM), and low
voltage flag (LVF) functions are also integrated to ensure safe
operation of the MCU as well as continuous monitoring of the
battery power supply.
The POR circuit is designed to handle all battery ramp rates
greater than 0.5 V per minute and guarantee full functional
operation of the Flash/EE memory-based MCU during power-on
and power-down cycles.
(INTERNAL SIGNAL)
ENABLE_PSM
RESET_CORE
ENABLE_LVF
REG_DVDD
POR_TRIP
VDD
3V TYP
Figure 28. Typical Power-On Cycle
2.6V
12V
20ms TYP
Rev. B | Page 65 of 140
As shown in Figure 28, once the supply voltage (on VDD),
reaches an operating voltage of 3 V, a POR signal keeps the
ARM core in reset for 20 ms. This ensures that the regulated
power supply voltage (REG_DVDD), supplied to the ARM core
and associated peripherals, is above the minimum operational
voltage to guarantee full functionality. A POR flag is set in the
RSTSTA MMR to indicate a POR reset event has occurred.
The ADuC7033 also features a power supply monitor (PSM)
function. When enabled through HVCFG0[3], the PSM con-
tinuously monitors the voltage at the VDD pin. If this voltage
drops below 6.0 V typical, the PSM flag is automatically asserted
and can, if the high voltage IRQ is enabled via IRQ/FIQEN[16],
generate a system interrupt. An example of this operation is
shown in Figure 28.
At voltages below the POR level, an additional low voltage flag
can be enabled (HVCFG0[2]). It can be used to indicate that the
contents of the SRAM remain valid after a reset event. The
operation of the low voltage flag is shown in Figure 28. When
enabled, the status of this bit can be monitored via HVMON[3].
If this bit is set, then the SRAM contents are valid. If this bit is
cleared, then the SRAM contents can be corrupted.
PSM TRIP 6.0V TYP
POR TRIP 3.0V TYP
LVF TRIP 2.1V TYP
ADuC7033