ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 131

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Detailed bit definitions for most of these MMRs have been
listed previously. In addition to the registers described in the
LIN MMR Description section, LHSCAP and LHSCMP are
registers that are required for the operation of the BSD
interface. Details of these registers follow.
LIN Hardware Synchronization Capture Register
Name:
Address:
Default Value:
Access:
Function:
LIN Hardware Synchronization Compare Register
Name:
Address:
Default Value:
Access:
Function:
BSD COMMUNICATIONS FRAME
To transfer data between a master and slave, or vice versa, the
construction of a BSD frame is required. A BSD frame contains
seven key components: pause/sync, direction bit, the slave
address, the register address, data, Parity Bit 1 (P1) and Parity
Bit 2 (P2), and the acknowledge from the slave.
If the master is transmitting data, then all bits except the
acknowledge bit, are transmitted by the master.
If the master is requesting data from the slave, the master
transmits the pause/sync, the direction bit, slave address,
register address, and P1 bits.
LHSCAP
0xFFFF0794
0x0000
Read only
The 16-bit, read only LHSCAP register holds
the last captured value of the internal LIN
synchronization timer (LHSVAL0). In BSD
mode, the LHSVAL0 is clocked directly from
an internal 5 MHz clock; its value is loaded
into the capture register on every falling edge
of the BSD bus.
LHSCMP
0xFFFF0798
0x0000
Read/write
The LHSCMP register is used to time BSD
output pulse widths. When enabled through
LHSCON0[5], a LIN interrupt is generated
when the value in LHSCAP equals the value
written in LHSCMP. This functionality allows
user code to determine how long a BSD
transmission bit (SYNC, 0, or 1) should be
asserted on the bus.
Rev. B | Page 131 of 140
Pause DIR
3 bits
The slave then transmits the data bytes, P2, and the
acknowledge in the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
The acknowledge is always transmitted by the slave to indicate
if the information was received or transmitted.
Table 97. BSD Protocol Description
BSD Example Pulse Widths
An example of the different pulse widths is shown in Figure 5 .
For each bit, the period for which the bus is held low defines
what type of bit it is. If the bit is a sync bit, the pulse is held low
for one bit. If the bit is a zero bit, the pulse is held low for three
bits. If the bit is a one bit, the pulse is held low for six bits.
If the master is transmitting data, the signal is held low for the
duration of the signal by the master. An example of a master
transmitting zero is shown in Figure 5 . If the slave is transmit-
ting data, the master pulls the bus low to begin communications.
The slave must then pull the bus low before t
hold the bus low until either t
the bus is released by the slave. An example of a slave trans-
mitting a zero is shown in Figure 5 .
PAUSE: ≥3 synchronization pulses.
DIR: signifies the direction of data transfer.
a.
b.
Slave Address.
Register Address: defines register to be read or written.
Bit 3 is set to write, cleared to read.
Data: 8-bit read-only receive register.
P1 and P2.
a.
b.
c.
d.
Acknowledge: zero (0) if transmission is successful.
BUS PULLED LOW
BY MASTER
t
1 bit 3 bits
SYNC
Zero (0) if master sends request.
One (1) if slave sends request.
P1 = 0 if even number of 1s in 8 previous bits.
P1 = 1 if odd number of 1s in 8 previous bits.
P2 = 0 if even number of 1s in data-word.
P2 = 1 if odd number of 1s in data-word.
t
t
0
1
t
Slave
Address
SYNC
Figure 54. BSD Master Transmitting Zero
t
0
Figure 53. BSD Bit Transmission
Register
Address
4 bits
0
or t
1
has elapsed, after which time
BUS RELEASED BY
MASTER AFTER
P1
1 bit 8 bits 1 bit 1 bit
SYNC
Data
t
0
ADuC7033
elapses and
P2
ACK