ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 48

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
15
14
13
12
11 to 5
4
3
ADuC7033
ADC MMR INTERFACE
The ADC is controlled and configured through a number of
MMRs described in detail in the following sections.
All bits defined in the top eight MSBs (Bits[15:8]) of the MMR
are used as flags only and do not generate interrupts. All bits
defined in the lower eight LSBs (Bits[7:0]) of this MMR are
logic OR’ e d to produce a single ADC interrupt to the MCU
core. In response to an ADC interrupt, user code should
interrogate the ADCSTA MMR to determine the source of
the interrupt. Each ADC interrupt source can be individually
masked via the ADCMSKI MMR described in ADC Interrupt
Mask Register section.
ADC Status Register
Name:
Address:
Default Value:
Access:
Function:
Table 35. ADCSTA MMR Bit Designations
ADCSTA
0xFFFF0500
0x0000
Read only
This read-only register holds general status information related to the mode of operation or current status of the
ADuC7033 ADCs.
Description
ADC Calibration Status.
Set automatically in hardware to indicate an ADC calibration cycle has been completed.
Cleared after ADCMDE is written to.
ADC Temperature Conversion Error.
Set automatically in hardware to indicate that a temperature conversion overrange or underrange has occurred. The
conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case.
Cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.
ADC Voltage Conversion Error.
Set automatically in hardware to indicate that a voltage conversion overrange or underrange has occurred. The
conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in
this case.
Cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
ADC Current Conversion Error.
Set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. The
conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in
this case.
Cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.
Not Used. These bits are reserved for future functionality and should not be monitored by user code.
Current Channel ADC Comparator Threshold. This bit is only valid if the current channel ADC comparator is enabled via
the ADCCFG MMR. Set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the
ADC0TH MMR. If the ADC threshold counter (ADC0TCL) is used, this bit is only set when the specified number of I-ADC
conversions equals the value in the ADC0THV MMR.
Current Channel ADC Overrange Bit. If the overrange detect function is enabled via the ADCCFG MMR, this bit is set by
hardware if the I-ADC input is grossly (>30% approximate) overrange. This bit is updated every 125 μs. When set, this bit
can only be cleared by software when ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the
ADC0CON MMR.
Rev. B | Page 48 of 140
All ADC result ready bits are cleared by a read of the ADC0DAT
MMR. If the current channel ADC is not enabled, all ADC
result ready bits are cleared by a read of the ADC1DAT or
ADC2DAT MMRs. To ensure that I-ADC and V/T-ADC
conversion data are synchronous, user code should first read
the ADC1DAT MMR and then the ADC0DAT MMR. New
ADC conversion results are not written to the ADCxDAT
MMRs unless the respective ADC result ready bits are first
cleared. The only exception to this rule is the data conversion
result updates when the ARM core is powered down. In this
mode, ADCxDAT registers always contain the most recent
ADC conversion result even though the ready bits have not
been cleared.