ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 124

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
Bit
7
6
5
4
3
2
1
0
Description
Sync Timer Stop Edge Type Bit.
Cleared to 0 by user code to stop the sync timer on the falling edge count configured through the LHSCON1[7:4]
register.
Set to 1 by user code to stop the sync timer on the rising edge count configured through the LHSCON1[7:4] register.
Mode of Operation Bit.
Cleared to 0 by user code to select LIN mode of operation.
Set to 1 by user code to select BSD mode of operation.
Enable Compare Interrupt Bit.
Cleared to 0 by user code to disable compare interrupts.
Set to 1 by user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (LIN synchronization bit timer)
= the value in the LHSCMP register. The LHS Compare Interrupt Bit LHSSTA[3] is set when this interrupt occurs. This
configuration is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be
transmitted.
Enable Stop Interrupt.
Cleared to 0 by user code to disable interrupts when a stop condition occurs.
Set to 1 by user code to generate an interrupt when a stop condition occurs.
Enable Start Interrupt.
Cleared to 0 by user code to disable interrupts when a start condition occurs.
Set to 1 by user code to generate an interrupt when a start condition occurs.
LIN Sync Enable Bit.
Cleared to 0 by user code to disable LHS functionality.
Set to 1 by user code to enable LHS functionality.
Edge Counter Clear Bit.
Set to 1 by user code to clear the internal edge counters in the LHS peripheral.
This bit is automatically cleared to 0 after a 15 μs delay.
LHS Reset Bit.
Set to 1 by user code to reset all LHS logic to default conditions.
This bit is automatically cleared to 0 after a 15 μs delay.
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