ADUC7033BCPZ-8L-RL Analog Devices Inc, ADUC7033BCPZ-8L-RL Datasheet - Page 130

• Manufacturer Part Number: ADUC7033BCPZ-8L-RL
• Description: IC MCU FLASH 96K ANLG I/O 48LFCS
• Manufacturer: Analog Devices Inc
• Type: Battery Managementr

Specifications of ADUC7033BCPZ-8L-RL

• Input Type: Logic
• Output Type: Logic
• Interface: UART, SPI
• Current - Supply: 20mA
• Mounting Type: Surface Mount
• Package / Case: *
• For Use With: EVAL-ADUC7033QSPZ - EVAL DEV QUICK START ADUC7033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7033
BIT SERIAL DEVICE (BSD) INTERFACE
BSD is a pulse-width modulated signal with three possible
states: sync, zero, and one. These are detailed, together with
their associated tolerances, in Table 96. The frame length is
19 bits and communication occurs at 1200 bps ± 3%.
Table 96. BSD Bit Level Description
Parameter
TxD Rate
Bit Encoding
BSD COMMUNICATION HARDWARE INTERFACE
The ADuC7033 emulates the BSD communication protocol
using a GPIO, an IRQ, and the LIN synchronization hardware,
all of which are under software control.
BSD RELATED MMRS
ADuC7033 emulates the BSD communication protocol using a
software (bit bang) interface with some hardware assistance
form LIN hardware synchronization logic. In effect, the
ADuC7033 BSD interface uses the following protocols:
•
•
t
t
t
SYNC
0
1
An internal GPIO signal (GPIO_12) that is routed to the
external LIN/BSD pin and is controlled directly by
software to generate 0s and 1s.
When reading bits, the LIN synchronization hardware uses
LHSVAL1 to count the width of the incoming pulses so
that user code can interpret the bits as sync, 0, or 1.
Min
1164
1/16
5/16
10/16
131kHz
LHS INTERRUPT
5MHz
IRQEN[7]
Typ
1200
2/16
6/16
12/16
ADuC7033
ADuC7033
HARDWARE
LHSVAL0
LHSVAL1
UART
LHS
RxD ENABLE
LHSCON0[8]
RxD
TxD
Max
1236
3/16
8/16
14/16
INTERRUPT
LOGIC
LHS
Figure 52. BSD I/O Hardware Interface
DISABLE
OUTPUT
Unit
bps
t
t
t
PERIOD
PERIOD
PERIOD
HVCFG0[1:0]
LIN MODE
FOUR LIN
INTERRUPT
SOURCES
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
Rev. B | Page 130 of 140
INPUT
VOLTAGE
THRESHOLD
REFERENCE
BPF
TRIP REFERENCE
SHORT-CIRCUIT
INTERNAL
•
The ADuC7033 MMRs required for BSD communication are as
follows:
LHSSTA:
LHSCON0:
LHSVAL0:
LHSCON1:
LHSVAL1:
LHSCAP:
LHSCMP:
IRQEN/CLR: Enable interrupt register.
FIQEN/CLR: Enable fast interrupt register.
GP2DAT:
GP2SET:
GP2CLR:
VDD
When writing bits, user code toggles a GPIO pin and uses
the LHSCAP and LHSCMP registers to time pulse widths
and generate an interrupt when the BSD output pulse
width has reached its required width.
PROTECTION
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
VOLTAGE
LIN ENABLE
(INTERNAL
HVCFG0[5]
OVER
PULL-UP)
EXTERNAL
LIN hardware sync status register.
LIN hardware sync control register.
LIN hardware sync Timer0 (16-bit timer).
LIN hardware sync edge setup register.
LIN sync break timer.
LIN sync capture register.
LIN sync compare register.
GPIO data register.
GPIO set register.
GPIO clear register.
IO_VSS
LIN PIN
SCR
VDD
MASTER ECU
PROTECTION
DIODE
MASTER ECU
PULL-UP
C
LOAD