ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 121

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9.7
9.7.1
9.7.2
9.7.3
9.7.4
8111C–MCU Wireless–09/09
Frequency Synthesizer (PLL)
Overview
RF Channel Selection
Frequency Agility
Calibration Loops
The main PLL features are:
The PLL generates the RF frequencies for the AT86RF231. During receive operation the fre-
quency synthesizer works as a local oscillator on the radio transceiver receive frequency, during
transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the
RF transmit signal. The frequency synthesizer is implemented as a fractional-N PLL.
Two calibration loops ensure correct PLL functionality within the specified operating limits.
The PLL is designed to support 16 channels in the 2.4 GHz ISM band with a channel spacing of
5 MHz according to IEEE 802.15.4. The center frequency of these channels is defined as
follows:
F
where k is the channel number.
The channel k is selected by register bits CHANNEL (register 0x08, PHY_CC_CA).
When the PLL is enabled during state transition from TRX_OFF to PLL_ON, the settling time is
typically t
calibration, refer to
indicated with an interrupt IRQ_0 (PLL_LOCK).
Switching between 2.4 GHz ISM band channels in PLL_ON or RX_ON states is typically done
within t
applications.
When starting the transmit procedure the PLL frequency is changed to the transmit frequency
within a period of t
settles back to the receive frequency within a period of t
not generate an interrupt IRQ_0 (PLL_LOCK) or IRQ_1 (PLL_UNLOCK) within these periods.
Due to variation of temperature, supply voltage and part-to-part variations of the radio trans-
ceiver the VCO characteristics may vary.
To ensure a stable operation, two automated control loops are implemented, center frequency
(CF) tuning and delay cell (DCU) calibration. Both calibration loops are initiated automatically
when the PLL is enabled during state transition from TRX_OFF to PLL_ON state. Additionally,
center frequency calibration is initiated when the PLL changes to a different channel center
frequency.
c
• Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4 GHz channels
• Autonomous calibration loops for stable operation within the operating range
• Two PLL-interrupts for status indication
• Fast PLL settling to support frequency hopping
= 2405 + 5 (k - 11) in [MHz], for k = 11, 12,..., 26
TR20
TR4
= 11 µs. This makes the radio transceiver highly suitable for frequency hopping
= 110 µs, including settling of the analog voltage regulator (AVREG) and PLL self
TR23
Table 7-2 on page 43
= 16 µs before starting the transmission. After the transmission the PLL
and
Figure 13-13 on page
TR24
= 32 µs. This frequency step does
168. A lock of the PLL is
AT86RF231
121